32-bit Version Research Articles

Enhancing Metaheuristic Optimization: A Novel Nature-Inspired Hybrid Approach Incorporating Selected Pseudorandom Number Generators

In this paper, a hybrid nature-inspired metaheuristic algorithm based on the Genetic Algorithm and the African Buffalo Optimization is proposed. The hybrid approach adaptively switches between the Genetic Algorithm and the African Buffalo Optimization during the optimization process, leveraging their respective strengths to improve performance. To improve randomness, the hybrid approach uses two high-quality pseudorandom number generators—the 64-bit and 32-bit versions of the SIMD-Oriented Fast Mersenne Twister. The effectiveness of the hybrid algorithm is evaluated on the NP-hard Container Relocation Problem, focusing on a test set of restricted Container Relocation Problems with higher complexity. The results show that the hybrid algorithm outperforms the individual Genetic Algorithm and the African Buffalo Optimization, which use standard pseudorandom number generators. The adaptive switch method allows the algorithm to adapt to different optimization problems and mitigate problems such as premature convergence and local optima. Moreover, the importance of pseudorandom number generator selection in metaheuristic algorithms is highlighted, as it directly affects the optimization results. The use of powerful pseudorandom number generators reduces the probability of premature convergence and local optima, leading to better optimization results. Overall, the research demonstrates the potential of hybrid metaheuristic approaches for solving complex optimization problems, which makes them relevant for scientific research and practical applications.

Hardware design and implementation of high-efficiency cube-root of complex numbers

This study presented an algorithm for fast hardware execution of complex cube root. In this algorithm, which is based on the Laurent series of ∛z function, first, the z-plane's numbers are mapped by using a rapid scaling and rotation operation to a pre-specified limited region, and then the sequences of the series are computed. The parameters of the algorithm are thoroughly analyzed and selected to achieve high precision. The algorithm has been implemented on a field programmable gate array-based platform using the Simulink HDL Coder tool and Xilinx ISE 14.7. In addition, the resource usage and speed parameters are carefully examined for the implementation of each step of the algorithm. Hardware was implemented in two 56-bit and 32-bit versions (for comparison). The 32-bit version occupies 140 slice Regs, 421 slice LUTs, and 5 DSP48s. The hardware with the capability of computing complex cube roots has appropriate specifications comparable with those of previous implementations of real cube root calculation on FPGA.

FEEDNet: a feature enhanced encoder-decoder LSTM network for nuclei instance segmentation for histopathological diagnosis

Objective. Automated cell nuclei segmentation is vital for the histopathological diagnosis of cancer. However, nuclei segmentation from ‘hematoxylin and eosin’ (HE) stained ‘whole slide images’ (WSIs) remains a challenge due to noise-induced intensity variations and uneven staining. The goal of this paper is to propose a novel deep learning model for accurately segmenting the nuclei in HE-stained WSIs. Approach. We introduce FEEDNet, a novel encoder-decoder network that uses LSTM units and ‘feature enhancement blocks’ (FE-blocks). Our proposed FE-block avoids the loss of location information incurred by pooling layers by concatenating the downsampled version of the original image to preserve pixel intensities. FEEDNet uses an LSTM unit to capture multi-channel representations compactly. Secondly, for datasets that provide class information, we train a multiclass segmentation model, which generates masks corresponding to each class at the output. Using this information, we generate more accurate binary masks than that generated by conventional binary segmentation models. Main results. We have thoroughly evaluated FEEDNet on CoNSeP, Kumar, and CPM-17 datasets. FEEDNet achieves the best value of PQ (panoptic quality) on CoNSeP and CPM-17 datasets and the second best value of PQ on the Kumar dataset. The 32-bit floating-point version of FEEDNet has a model size of 64.90 MB. With INT8 quantization, the model size reduces to only 16.51 MB, with a negligible loss in predictive performance on Kumar and CPM-17 datasets and a minor loss on the CoNSeP dataset. Significance. Our proposed idea of generalized class-aware binary segmentation is shown to be accurate on a variety of datasets. FEEDNet has a smaller model size than the previous nuclei segmentation networks, which makes it suitable for execution on memory-constrained edge devices. The state-of-the-art predictive performance of FEEDNet makes it the most preferred network. The source code can be obtained from https://github.com/CandleLabAI/FEEDNet.

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

One of the main decisions when making a digital design is which arithmetic is going to be used. The arithmetic determines the hardware resources needed and the latency of every operation. This is especially important in real-time applications like HIL (Hardware-in-the-loop), where a real-time simulation of a plant—power converter, mechanical system, or any other complex system—is accomplished. While a fixed-point gets optimal implementations, using considerably fewer resources and allowing smaller simulation steps, its use is very restricted to very specific applications, as its design effort is quite high. On the other side, IEEE-754 floating-point may have resolution problems in case of the 32-bit version, and excessive hardware usage in case of the 64-bit version. This paper presents LOCOFloat, a low-cost floating-point format designed for FPGA applications. Its key features are soft normalization of the results, using significand and exponent fields in two’s complement. This paper shows the implementation of addition, subtraction and multiplication of the proposed format. Both IEEE-754 versions and LOCOFloat are compared in this paper, implementing a HIL model of a buck converter. Although the application example is a HIL simulator, other applications could take benefit from the proposed format. Results show that LOCOFloat is as accurate as 64-bit floating-point, while reducing the use of DSPs blocks by 84 % .

Laius: an energy-efficient FPGA CNN accelerator with the support of a fixed-point training framework

With the development of convolutional neural networks (CNNs), their high computational complexity and energy consumption become significant problems. Many CNN inference accelerators are proposed to reduce the consumption. Most of them are based on 32-bit float-point matrix multiplication, where the data precision is over-provisioned. This paper presents Laius, an 8-bit fixed-point LeNet inference engine implemented on FPGA. To achieve low-precision computation and storage, we introduce our fixed-point training framework called FixCaffe. To economise FPGA resources, we proposed a methodology to find the optimal bit-length for weight and bias in LeNet. We use optimisations of pipelining, tiling, and theoretical analysis to improve the performance. Experiment results show that Laius achieves 44.9 Gops throughputs. Moreover, with only 1% accuracy loss, 8-bit Laius largely reduces 31.43% in delay, 87.01% in LUT consumption, 66.50% in BRAM consumption, 65.11% in DSP consumption and 47.95% in power compared to the 32-bit version with the same structure.

Efficient and secure software implementations of Fantomas

In this paper, the efficient software implementation and side-channel resistance of the LS-Design construction are studied through a series of software implementations of the Fantomas block cipher, one of its most prominent instantiations. Target platforms include resource-constrained ARM devices like the Cortex-M3 and M4, and more powerful processors such as the ARM Cortex-A15 and modern Intel platforms. The implementations span a broad range of characteristics: 32-bit and 64-bit versions, unprotected and side-channel resistant, and vectorized code for NEON and SSE instruction sets. Our results improve the state of the art substantially, in terms of both efficiency and compactness, by making use of novel algorithmic techniques and features specific to the target platform. We finish by proposing and prototyping instruction set extensions to reduce by half the performance penalty of the introduced side-channel countermeasures.

Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture

Abstract Chip Multiprocessors (CMP) have emerged during last decades as a very attractive solution in using the ever-increasing on-chip transistor count. However, classical parallelization techniques failed to fully exploit parallelization from existing sequential applications due to false data dependencies. This paper focuses on the Thread-level Speculation (TLS) technique, an alternative way to exploit the transistor budget in a CMP. With TLS, even possibly data dependent threads can run in parallel as long as the semantics of the sequential execution is preserved. A special hardware support monitors the actual data dependencies between threads at run time and, if they are violated, misspeculation effects are undone usually through replay. This kind of system is known as speculative CMP. However, the TLS mechanism requires complex protocols that integrate cache coherence and speculation to maintain program order among multiple versions of data. Current TLS protocol evaluations are usually inadequate because they are not done low-level enough. A realistic evaluation of speculative CMPs requires either to be performed on a real hardware or very detailed cycle-accurate simulator models. In this paper we are particularly focused on a low-level evaluation of the write-invalidate TLS protocol Speculation Integrated with Snoopy Coherence (SISC) protocol proposed in [1] . This evaluation relies on cycle-level simulation environment with detailed cycle-level cache memories, cache controller and system bus. On top of this, a speculative four core architecture is simulated and three new modules (Scheduler, Squash Arbiter and Supplier Arbiter) are provided to support low-level implementation of the SISC protocol. The overall cost of the SISC protocol is evaluated by means of CACTI tool for the three different domains: the access latency cost, the area cost, and the power cost. The evaluation goal was to keep the cache access time to remain below cycle latency as well as the area and power overheads below an acceptable budget overhead. The SISC protocol has been compared against regular MESI-based architecture in both 32-bit and 64-bit versions. We kept the cache access time below the cycle latency, and we managed to keep both data cache area and static power overheads respectively below 32% and 35%.

VSEARCH: a versatile open source tool for metagenomics.

BackgroundVSEARCH is an open source and free of charge multithreaded 64-bit tool for processing and preparing metagenomics, genomics and population genomics nucleotide sequence data. It is designed as an alternative to the widely used USEARCH tool (Edgar, 2010) for which the source code is not publicly available, algorithm details are only rudimentarily described, and only a memory-confined 32-bit version is freely available for academic use.MethodsWhen searching nucleotide sequences, VSEARCH uses a fast heuristic based on words shared by the query and target sequences in order to quickly identify similar sequences, a similar strategy is probably used in USEARCH. VSEARCH then performs optimal global sequence alignment of the query against potential target sequences, using full dynamic programming instead of the seed-and-extend heuristic used by USEARCH. Pairwise alignments are computed in parallel using vectorisation and multiple threads.ResultsVSEARCH includes most commands for analysing nucleotide sequences available in USEARCH version 7 and several of those available in USEARCH version 8, including searching (exact or based on global alignment), clustering by similarity (using length pre-sorting, abundance pre-sorting or a user-defined order), chimera detection (reference-based or de novo), dereplication (full length or prefix), pairwise alignment, reverse complementation, sorting, and subsampling. VSEARCH also includes commands for FASTQ file processing, i.e., format detection, filtering, read quality statistics, and merging of paired reads. Furthermore, VSEARCH extends functionality with several new commands and improvements, including shuffling, rereplication, masking of low-complexity sequences with the well-known DUST algorithm, a choice among different similarity definitions, and FASTQ file format conversion. VSEARCH is here shown to be more accurate than USEARCH when performing searching, clustering, chimera detection and subsampling, while on a par with USEARCH for paired-ends read merging. VSEARCH is slower than USEARCH when performing clustering and chimera detection, but significantly faster when performing paired-end reads merging and dereplication. VSEARCH is available at https://github.com/torognes/vsearch under either the BSD 2-clause license or the GNU General Public License version 3.0.DiscussionVSEARCH has been shown to be a fast, accurate and full-fledged alternative to USEARCH. A free and open-source versatile tool for sequence analysis is now available to the metagenomics community.

IEEE 754 부동 소수점 32비트 float 변수의 Morton Code 변환 분석

GPU 기반 병렬처리에서 대규모 데이터의 인접 정보 검색(nearest neighbor search)에서 Morton code의 역할이 점점 더 중요하게 부각되고 있으며 그 응용 사례도 점차 증가하고 있다. 본 논문에서는 Tero Karras가 제안한 float 형 변수에 기반한 <TEX>$[0,1</TEX><TEX>]</TEX><TEX>^3$</TEX> 공간 내의 3차원 기하 정보를 32비트 unsigned int형 Morton code로 변경하는 기존의 방법을 논의하고 그 기하학적인 의미를 분석함으로써, 보다 높은 해상도를 구현할 수 있는 64비트 unsigned long long형의 Morton code 변환 알고리듬을 제안한다. 제안하는 알고리듬은 GPU에서 구현되었을 때 CPU에서 실행하는 것보다 약 1000배 수준의 성능 향상을 달성한다. Morton codes play important roles in many parallel GPU applications for the nearest neighbor (NN) search in huge data and queries with its applications growing. This paper discusses and analyzes the meaning of Tero Karras's 32-bit 'unsigned int' Morton code algorithm for three-dimensional spatial information in <TEX>$[0,1</TEX><TEX>]</TEX><TEX>^3$</TEX> and its geometric implications. Based on this, this paper proposes 64-bit 'unsigned long long' version of Morton code and compares the results in both CPU vs. GPU and 32-bit vs. 64-bit versions. The proposed GPU algorithm runs around 1000 times faster than the CPU version.

Advanced Measurements of the Aggregation Capability of the MPT Network Layer Multipath Communication Library

The MPT network layer multipath communicationlibrary is a novel solution for several problems including IPv6transition, reliable data transmission using TCP, real-time transmissionusing UDP and also wireless network layer routingproblems. MPT can provide an IPv4 or an IPv6 tunnel overone or more IPv4 or IPv6 communication channels. MPT canalso aggregate the capacity of multiple physical channels. In thispaper, the channel aggregation capability of the MPT libraryis measured up to twelve 100Mbps speed channels. Differentscenarios are used: both IPv4 and IPv6 are used as the underlyingand also as the encapsulated protocols and also both UDP andTCP are used as transport protocols. In addition, measurementsare taken with both 32-bit and 64-bit version of the MPT library.In all cases, the number of the physical channels is increased from1 to 12 and the aggregated throughput is measured.

Instruction set architectural guidelines for embedded packet-processing engines

This paper presents instruction set architectural guidelines for improving general-purpose embedded processors to optimally accommodate packet-processing applications. Similar to other embedded processors such as media processors, packet-processing engines are deployed in embedded applications, where cost and power are as important as performance. In this domain, the growing demands for higher bandwidth and performance besides the ongoing development of new networking protocols and applications call for flexible power- and performance-optimized engines. The instruction set architectural guidelines are extracted from an exhaustive simulation-based profile-driven quantitative analysis of different packet-processing workloads on 32-bit versions of two well-known general-purpose processors, ARM and MIPS. This extensive study has revealed the main performance challenges and tradeoffs in development of evolution path for survival of such general-purpose processors with optimum accommodation of packet-processing functions for future switching-intensive applications. Architectural guidelines include types of instructions, branch offset size, displacement and immediate addressing modes for memory access along with the effective size of these fields, data types of memory operations, and also new branch instructions. The effectiveness of the proposed guidelines is evaluated with the development of a retargetable compilation and simulation framework. Developing the HDL model of the optimized base processor for networking applications and using a logic synthesis tool, we show that enhanced area, power, delay, and power per watt measures are achieved.

English

The variations of day light intensity must be taken into account to recognize the color of the agriculture product when using camera vision system. In this study, the development of outdoor image analysis for oil palm fruit fresh bunches (FFB) was developed to analyses image of oil palm FFB. The software analysis will generates the mathematical model and correlation factor between the light intensity in relation to value of FFB from Red, Green and Blue component (RGB) of image taken. The visual basic programming language was used. An Excel worksheet programming software was developed to draw a chart and modify the charts location and dimensions. The API (Application Programming Interface) called GDI32 (Graphic Device Interface: 32-bit version) was applied to read and manipulate the pixel value of image. The software automation technique was used in the development of outdoor image analysis for agriculture product. The automation concept is to describe the automatic generation of the software to manipulate the data for producing the graph, mathematical analysis and equation, automatically from a bundle of data collected by only a click of mouse button. The result generated was used to develop mathematical model for color-based recognition for outdoor image of agriculture product. Linear regression function was used to find the equation of mathematical model for outdoors image analysis. To find the best equation of mathematical model, various trendline of data manipulation can be chosen manually from option provided in Microsoft Excel. The images of FFB were taken by using sony digital camera Handycam at various times of day from morning to afternoon in the oil palm plantation. Keywords - Outdoors Vision System, Colour Recognition, Software Automation, Oil Palm FFB

Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia

We consider the implementation of 16-bit floating point instructions on a Pentium 4 and a PowerPC G5 for image and media processing. By measuring the execution time of bench-marks with these new simulated instructions, we show that significant speed-ups are obtained compared to 32-bit FP versions. For image processing, the speed-up both comes from doubling the number ofoperations per SIMD instruction and the better cache behavior with byte storage. For data stream processing with arrays of structures, the speed-up comes from the wider SIMD instructions.

A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine–cosine generators

The CORDIC algorithm has been readily used to decimate trigonometric and hyperbolic functions with simple shift and add operations. Despite further refinements in terms of circuit latency and performance of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, the iterative nature remains to be the major bottleneck for further optimisation. In this paper, a novel approach for the pre-computation of the polarity of micro-rotations has been proposed to eliminate the iterative process during sine/cosine computations. This approach to determine the signed digits lends well towards realising high-speed sine/cosine functions. It relies on a new technique, called Split Decomposition Algorithm, devised for the VLSI efficient implementation of the pre-computation of the polarity of micro-rotations. A ROM less architecture for the pre-computation of the polarity of micro-rotations has been devised with the help of a new algorithm that exploits certain properties of the signed digits. The architectures for 24-bit and 32-bit versions were implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesised with 0.35μ technology library and the area-time measures are provided.

Advances in automatic powder indexing: An enhanced 32-bit version of the Crysfire suite

Advances in automatic powder indexing: An enhanced 32-bit version of the Crysfire suite

Developing rectification programs for small computers

A series of programs, widely known by the name aerial, is available for the rectification of oblique aerial photographs. The programs have developed over many years, in response to users' needs and increasing computer power. In recent years two major modifications have been introduced: a version to rectify raster images under 16-bit versions of Microsoft Windows; and a version with an extended range of facilities to run under 32-bit versions of Windows. The historical development of the programs is described, and the objectives of the most recent versions are explained. The operation of the programs is illustrated with an extended example from recent practice. Copyright © 2000 John Wiley & Sons, Ltd.

Software Reviews : WinAMOS Publisher: SmallWaters Statistical Consulting and Computing, 1507 E. 53 St., #452, Chicago, IL 60615; telephone: 312-667-8635; fax: 312-955-6252; e-mail: smallwaters @acm.org; URL: http : //www. smallwaters. com. Year of Publication: 1996 Version Reviewed: 3.51 System Requirements: PC with 80386 processor or higher, 6 MB RAM or greater, mouse, 4.9 MB free hard disk space, Windows 3.1

AMOS implements structural modeling. Conceived by James Arbuckle, a psychometrician, as a vehicle for teaching causal analysis, AMOS has evolved into a powerful research environment that eases even nonstatisticians into this important arsenal of tools. AMOS supports structural modeling through maximum likelihood, unweighted least- squares, generalized least squares, Browne's asymptotically distribution-free criterion, and scale-free least-squares. It uses built-in bootstrapping (resampling) to derive standard errors and confidence intervals for sample means, variances, covariances, correlations, and other estimates. Given the researcher's specification of a path diagram, AMOS estimates the path parameters in diagrammatic form, which can be exported to either word processors or graphics programs. The AMOS environment also provides a graphical method for teaching statistics, from hypothesis tests of means through analysis of covariance, multiple regression, and factor analysis, all within the unifying framework of the structural equation modeling perspective.

GeoSight fact finder, GIS based software package

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.

A high-performance software implementation of the Data Encryption Algorithm (DEA)

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.

Data encryption unit

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.