32-bit Instruction Research Articles

Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

Thumb-2 명령어 집합 구조의 병렬 분기 명령어 확장

본 논문에서는 Thumb-2 명령어 집합 구조의 성능을 개선하기 위하여 분기 명령어와 사용 빈도가 높은 명령어를 동시에 실행하는 병렬 분기 명령어 집합을 제시한다. 제시된 기법에서는 16비트 분기 명령어와 사용 빈도가 높은 16비트 LOAD, ADD, MOV, STORE, SUB 명령어를 각각 결합하는 새로운 32비트 명령어를 도입한다. 새로운 명령어의 인코딩 공간을 제공하기 위해 사용 빈도가 낮은 기존 명령어의 레지스터 필드에 사용되는 비트 수를 줄이고 이를 통해 절약된 비트들을 이용하여 병렬 분기 명령어를 인코딩한다. 실험 결과, 제시된 방법은 코드 크기를 증가시키지 않고 전통적인 방식과 비교하여 평균 8.0%의 성능을 향상시킨다. In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

Reducing instruction bit-width for low-power VLIW architectures

VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bit-width restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.

Code Size Reduction in Embedded Systems with Redesigned ISA for RISC Processors

Reducing the size of a program is a major goal in modern embedded systems. Large code occupies more space in the Chip and also causes higher power consumption because of increased memory traffic. In this paper, a revised architecture is proposed for embedded processors by replacing the Loadstore Architecture with Register-Memory Architecture for selected instructions. Analysis of RISC object code for Embedded Applications, using an offline tool developed by the authors, establishes the scope for a new class of processor exclusively for embedded applications. We have used this tool to simulate Register-Memory Architecture for MIPS processor. Based on the results, MIPS processor's instruction set is enhanced with 12 new instructions of Register-Memory Architecture. Experimental results for MiBench Benchmark programs with Register-Memory Architecture Simulation reveal that code size reduction up to 22% can be achieved with modified MIPS Architecture. This is also applicable for microMIPS processor that claims 35% code space saving with 16-bit instructions, thus offering a total of over 55% code space reduction compared to MIPS32 Architecture, for embedded systems. Equivalent memory reduction achieved is very significant for Embedded Systems built using SOCs. Processor design modifications, required at microarchitecture level, are also identified. Other additional features that can be combined with Register-Memory Architecture for an efficient embedded processor are identified. General Terms Computer Architecture, Embedded Systems

AMEX: 16비트 Thumb 명령어 집합 구조의 주소 지정 방식 확장

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

OpenRISC 프로세서를 위한 압축 명령어 집합 구조

본 논문에서는 OpenRISC 프로세서의 코드 크기를 저감하는 새로운 압축 명령어 집합 구조를 제시한다. 새로운 명령어와 형식은 기존 명령어들의 사용 빈도와 용법에 대한 프로파일 정보에 의해 결정된다. 제시된 기법에서는 기존의 32비트 명령어들과 연속적인 명령어들을 각각 대체하는 새로운 16비트 명령어와 32비트 명령어를 도입한다. 제시된 명령어는 세 유형으로 분류할 수 있다. 첫 번째는 사용 빈도가 높은 기존의 덧셈, 로드, 저장, 분기 명령어 등의 32비트 명령어들을 대체하는 새로운 16비트 명령어들이다. 두 번째 유형은 사용 빈도가 높은 두 개의 연속적인 로드 명령어, 두 개의 연속적인 저장 명령어, 32비트 데이터 이동 명령어를 압축하는 새로운 32비트 명령어들이다. 마지막으로 함수 프롤로그와 에필로그 명령어들을 각각 하나로 압축하는 두 개의 새로운 32비트 명령어가 제시된다. 추가된 명령어들을 디코딩하기 위해서 OpenRISC 하드웨어 디코더 부분이 확장된다. OpenRISC 1200프로세서에서 실험을 수행한 결과, 성능 저하 없이 30.4%의 코드 크기를 절감한다. To achieve efficient code size reduction, this paper proposes a new compressed instruction set architecture for the OpenRISC architecture. The new instructions and their corresponding formats are designed by the profiling information of the existing instruction usage. New 16-bit instructions and 32-bit instructions are proposed to compressed the existing 32-bit instructions and instruction sequences, respectively. The proposed instructions can be classified into three types. The first is the new 16-bit instructions for the frequent normal 32-bit instructions such as add, load, store, branch, and jump instructions. The second type is the new 32-bit instructions for the consecutive two load instructions, two store instructions, and 32-bit data mov instructions. Finally, two new 32-bit instructions are proposed to compress function prolog and epilog code, respectively. OpenRISC hardware decoder is extended to support the new instructions. Experiments show that the efficiency of code size reduction improves by an average of 30.4% when compared to the OR1200 instruction set architecture without loss of execution performance.

16비트 명령어 기반 프로세서를 위한 페어 레지스터 할당 알고리즘

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

Simulation and Verification of Self Test 16Bit Processor

paper presents the design and verification of 16 bit processor. The Booth multiplier and restoring division are integrated in to the ALU of the proposed processor. The processor is described in structural level to verify the general understanding of the system. The processor has 16-bit instruction based on three different format R-format, I-format and J-format. The control unit generates all the control signals needed to control the coordination among the entire component of the processor. All the modules in the design are coded in VHDL (very high speed integrated circuit hardware description language) to ease the description, verification, simulation and hardware implementation. The design entry, synthesis, and simulation of processor are done by using Xilinx ISE 10.1 software and implemented on XC2S200-6pq208 Spartan-II FPGA device.

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

We built a 12.4mm × 12.4mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4GB), but chip-total memory usage will exceed 4GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.

Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)

For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32/16 bit ISA. We also show that the code compression obtained by this “dual instruction set” technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.

Dynamic coalescing for 16-bit instructions

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

The performance and energy consumption of embedded real-time operating systems

We present the modelling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: /spl mu/C/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multirate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Our simulations show what happens when RTOSs are pushed beyond their limits and they depict situations in which unexpected interrupts or unaccounted-for task invocations disrupt timing, even when the CPU is lightly loaded. In general, there appears no clear winner in timing accuracy between preemptive systems and cooperative systems. The power-consumption measurements show that RTOS overhead is a factor of two to four higher than it needs to be, compared to the energy consumption of the minimal scheduler. In addition, poorly designed idle loops can cause the system to double its energy consumption-energy that could be saved by a simple hardware sleep mechanism.

Enhancing the performance of 16-bit code using augmenting instructions

In the embedded domain, memory usage and energy consumption are critical constraints. Dual width instruction set embedded processors such as the ARM provide a 16-bit instruction set in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and I-cache energy savings at the cost of performance. We have observed that throughout 16-bit Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed an approach which uses combination of compiler and architectural support to exploit the above property for improving performance of 16-bit code. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). The task of the compiler is to identify pairs of Thumb instructions that can be safely combined and executed as single ARM instructions. The compiler replaces such pairs of Thumb instructions by AX+Thumb instruction pairs. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. Thus, using AX instructions, the compiler can both generate compact 16-bit code and provide hardware with information needed to produce better performing 32-bit code.

A network flow approach to memory bandwidth utilization in embedded DSP core processors

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, 16-bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data-memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher-memory bandwidths without increasing cost.

SH-5: the 64 bit superH architecture

A collaborative effort of Hitachi and STMicroelectronics, the SH-5 is the latest member of the SuperH microprocessor series. Its CPU core is the first implementation of a new instruction set architecture consisting of 32-bit instructions, 64-bit registers, SIMD (single-instruction, multiple-data) instructions for multimedia applications, and a compatibility mode supporting the 16-bit SuperH instruction set. Embodying an emerging philosophy of embedded-core design, the SH-5 provides a platform for a wide range of applications: set top cable boxes, digital TV, voice over IP (Internet telephony), network processing, PDAs (personal digital assistants), Internet appliances, in-car information systems, game machines, and so on. A single cost-effective, optimum design that will cater to the requirements of such a wide range of applications is not feasible. So the SH-5 core supports a carefully selected set of functions critical to meeting the performance, power, and code-size requirements of these applications. At the same time, it: provides features that ease integration into a system on chip (SOC) that uses application-specific hardware modules to cater to specific requirements.

Neural Image Processing Strategies Applied in Real-Time Pattern Recognition

Samples from stochastic signals with sufficient complexity need to agree in only a small portion of their details in order to justify rejection of the hypothesis that they arise from independent sources. The failure of a statistical test of independence can thereby serve as a basis for recognizing complex patterns, provided that they possess enough degrees-of-freedom and a representation can be found which extracts them. This paper describes a pattern recognition application of this statistical principle when conjoined with an image coding strategy that appears to be the representation used in the visual cortex of the mammalian brain. The result is a practical system for automatic real-time personal identification, based upon imaging the random texture visible at some distance in the iris of a person's eye. The recognition algorithm demodulates the iris texture with complex-valued 2D Gabor wavelets, and coarsely quantizes the resulting phasors to build a 256-byte ‘IrisCode’ whose entropy is roughly 173 bits. Ergodicity and commensurability facilitate extremely rapid comparisons of entire IrisCodes using 32-bit parallel integer-XOR instructions Recognition decisions are achieved with astronomic confidence levels, and with exhaustive database searches conducted at the rate of about 10,000 persons/s.

ARM7TDMI power consumption

Portable and handheld products require processors that consume less power than those in desktop and other powered applications. As a result, designers must analyze power use in the early stage of design both at the circuit and system levels. RISC processors, such as our ARM7TDMI, have both strengths and weaknesses as far as power consumption is concerned. From a system perspective, RISC processors should consume more power than CISC processors since RISCs need to be fed with an instruction virtually every cycle. RISC processors usually have a fixed 32bit instruction format, which forces a 32-bit memory access every cycle. Thus, the processor consumes power both in accessing the memory and in driving 32 address and 32 data wires across a PCB.

The RISC processor DMN-6: a unified data-control flow architecture

This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concentrates all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control signal generation for an integer functional unit. This is obtained by implementing a number of queue registers of different deepness around the datapath unit. These queues will control an assigned logic corresponding to a stage in the pipeline. The architecture reduces even more the complexity of a pipelined program execution. The main features are : Load/Store architecture, 4-stage pipeline, integer arithmetic, sixteen byte registers, internal separate data and instruction main memories, thirteen 16-bit instruction words.

16-bit vs. 32-bit instructions for pipelined microprocessors

In any stored-program computer system, information is constantly transferred between the memory and the instruction processor. Machine instructions are a major portion of this traffic. Since transfer bandwidth is a limited resource, inefficiency in the encoding of instruction information (low code density) can have definite hardware and performance costs. Starting with a parameterized baseline RISC design, we compare performance for two instruction encodings for the same instruction processing core. One is a variant of DLX, a typical 32-bit RISC instruction set. The other is a 16-bit format which sacrifices some expressive power while retaining essential RISC features. Using optimizing compilers and software simulation, we measure code density and path length for a suite of benchmark programs, relating performance differences to specific instruction set features. We measure time to completion performance while varying memory latency and instruction cache size parameters. The 16-bit format is shown to have significant cost-performance advantages over the 32-bit format under typical memory system performance constraints.

A programmable floating-point cell for systolic signal processing

The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.