Double-gate Research Articles

Linearity and intermodulation distortion analysis of single and dual metal gate junctionless transistor

Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity and intermodulation distortion of single metal (SMG) and double metal (DMG) double gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects of temperature fluctuation, gate length variation, and gate material engineering on the linearity performance of both devices are also studied. A few significant figures of merit, including Voltage Intercept Point 2 (VIP2), Voltage Intercept Point 3 (VIP3), Third Order Intercept Power (IIP3), 1 dB Compression Point (P1dB), Third Order Intermodulation Distortion (IMD3), and the transconductance derivative parameters First Order Transconductance (gm1), Second Order Transconductance (gm2), and Third Order Transconductance (gm3) are used to assess the device linearity and intermodulation distortion of SMG and DMG JLT's. The findings show that higher VIP2, VIP3, IIP3, 1-dB compression point and lower gm3, IMD3 values are obtained for the SMG JLT device when compared to its counterpart DMG JLT. SMG JLT, which assures strong linearity and low distortion.

Novel double deck gate field plate structure on a normally-off AlGaN/GaN HEMT- An extensive analysis

A novel double deck gate field plate structure on a normally-off AlGaN/GaN HEMT is proposed and compared with the conventional no field plate structure. Several passivation materials with relative permittivity (εr) ranging from 3.9 to 22 is taken into consideration to study the breakdown and DC characteristics. The implementation of field plate along with a higher εr material helps in improving breakdown voltage (VBr) as they both decrease the electric field at the gate's drain edge. Aiming device optimization several field plate configurations are studied including tri field plate structure, dual field plate structures and single gate FP structure. Extensive analysis in these structures are done with different lengths of the field plates and distance between source and drain. Distance between source and drain (LSD) is varied from 8.4 to 13.4 μm, source FP lengths (LS_FP) varies from 1 to 7 μm, gate FP lengths (LG_FP) varies from 0.9 to 2.3 μm and drain FP lengths (LD_FP) varies from 0.2 to 4.9 μm. In all scenarios with varying LSD, VBr rises with increasing LSD. For source, gate and drain FP lengths variation, VBr decreases as it gets longer because the electric field becomes very high. As the distance between the FP edge and the drain becomes narrower with increase in FP lengths, the breakdown occurs at lower voltage. At LSD 13.4 μm, this novel double deck gate FP structure with conventional drain field plate structure gives highest VBr of 1660 V and a small Ron of 2.39 Ω mm as compared to other structures. It also outperforms the other three structures in FT (9.84 GHz) at this particular LSD. Analysis of the simulated structures shows that the union of gate-drain field plate boosts the VBr while decreasing the Ron, resulting in improved electrical performance and a wider application range.

Mimicking the retinal neuron functions by a photoresponsive single transistor with a double gate

To realize a low-cost neuromorphic visual system, employing an artificial neuron capable of mimicking the retinal neuron functions is essential. A photoresponsive single transistor neuron composed of a vertical silicon nanowire is proposed. Similar to retinal neurons, various photoresponsive characteristics of the single transistor neuron can be modulated by light intensity as well as wavelength and have a high responsivity to green light like the human eye. The device is designed with a cylindrical surrounding double-gate structure, enclosed by an independently controlled outer gate and inner gate. The outer gate has the function of selectively inhibiting neuron activity, which can mimic lateral inhibition of amacrine cells to ganglion cells, and the inner gate can be utilized for the adjustment of the firing threshold voltage, which can be used to mimic the regulation of photoresponsivity by horizontal cells for adaptive visual perception. Furthermore, a myelination function that controls the speed of information transmission is obtained according to the inherent asymmetric source/drain structure of a vertical silicon nanowire. This work can enable photoresponsive neuronal function using only a single transistor, providing a promising hardware implementation for building miniaturized neuromorphic vision systems at low cost.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Miller capacitance reduction in negative capacitance TFETs

ABSTRACT A dielectric stacked hetero-gate topology is proposed to reduce the Miller capacitance in a negative capacitance double gate TFET. An analytical charge-based model is introduced for the analysis of the terminal capacitance behaviour of the device. Charge and capacitance models are developed using the surface potential modelling approach by solving the Poisson Equation. The proposed closed-form charge model is SPICE-compatible and can be used for circuit simulations. The model accuracy is validated by combining one-dimensional Landau–Khalatnikov equation with the two-dimensional simulations of the double gate stacked-hetero-gate tunnel field effect transistor. The model shows excellent agreement with device simulations. The proposed topology exhibits Miller capacitance reduction of 30% which results in the gain band width product improvement of 43% more than the stacked homo-gate counterpart.

Control of the unscreened modes in AlGaN/GaN terahertz plasmonic crystals

Unscreened (ungated) plasmons in large-area grating-gate AlGaN/GaN heterostructures were studied experimentally by Fourier-transform spectroscopy. Special attention was paid to the recently discovered THz plasmonic crystal modes observed at totally depleted gated regions when plasma oscillations were localized only in ungated parts of the grating-gate structures. The frequency of these modes is still gate voltage-dependent in the limited range due to the depletion of the ungated parts located close to the gate edges. Double gate structures with an additional bottom gate were fabricated and studied to improve the gate voltage tunability of the unscreened plasmons. Since this gate is located deep below the channel, the plasmons behaved as ungated ones, but their frequency still could be tuned by this bottom gate. We show that the combined effect of the top and bottom gates allows the efficient tuning of terahertz frequencies of unscreened modes in the grating-gate AlGaN/GaN plasmonic crystals.

Performance assessment of Si based dual metal double gate vertical TFET biosensor

This piece of work highlights the application of dual-metal double-gate VTFET as label free biosensor having enhanced switching ratio, current driving capability and sub-threshold swing and consequently high sensitivity. The use of dual-material namely tunneling gate and auxiliary gate in this device leads to high switching ratio (ION/IOFF) and low sub-threshold swing (SS). In order to observe outcome of this suggested biosensor, various biomolecules dielectric constant have been considered and examined with respect to electric field, energy band diagram, drain current characteristics and sub-threshold potential profile. Neutral biomolecules with a higher dielectric constant exhibits greater drain current sensitivity against biomolecules having lower dielectric constant. Here effect of cavity interface charge on the sensitivity performance of the proposed biosensor device is also verified. This fabrication feasible homo vertical TFET based biosensor gives best sensitivity performance for K = 12, both for the current (5.44 × 105) and transconductance (3.14 × 105) with the minimal sub-threshold swing of 9.9 mV/decade. Silvaco, a commercially accessible TCAD tool is used to investigate the proposed structure.

Study of Acoustic Emission from the Gate of Gallium Nitride High Electron Mobility Transistors

Nitrides are the leading semiconductor material used for the fabrication of high electron mobility transistors (HEMTs). They exhibit piezoelectric properties, which, coupled with their high mechanical stiffness, expand their versatile applications into the fabrication of piezoelectric devices. Today, due to advances in device technology that result in a reduction in the size of individual transistor elements and due to increased structural complexity (e.g., multi-gate transistors), the integration of piezoelectric materials into HEMTs leads to an interesting occurrence, namely acoustic emission from the transistor gate due to piezoelectric effects. This could affect the device’s performance, reliability, and durability. However, this phenomenon has not yet been comprehensively described. This paper aims to examine this overlooked aspect of AlGaN/GaN HEMT operation, that is, the acoustic emission from the gate region of the device induced by piezoelectric effects. For this purpose, dedicated test structures were designed, consisting of two narrow 1.7 μm-wide metallization strips placed at distances ranging from 5 μm to 200 μm fabricated in AlGaN/GaN heterostructures to simulate and examine the gate behavior of the HEMT transistor. For comparison, the test device structures were also fabricated on sapphire, which is not a piezoelectric material. Measurements of acoustic and electrical interactions in the microwave range were carried out using the “on wafer” method with Picoprobe’s signal–ground–signal (SGS)-type microwave probes. The dependence of reflectance |S11| and transmittance |S21| vs. frequency was investigated, and the coupling capacitance was determined. An equivalent circuit model of the test structure was developed, and finite element method simulation was performed to study the distribution of the acoustic wave in the nitride layers and substrate for different frequencies using Comsol Multiphysics software. At frequencies up to 2–3 GHz, the formation of volume waves and a surface wave, capable of propagating over long distances (in the order of tens of micrometers) was observed. At higher frequencies, the resulting distribution of displacements as a result of numerous reflections and interferences was more complicated. However, there was always the possibility of a surface wave occurrence, even at large distances from the excitation source. At small gate distances, electrical interactions dominate. Above 100 µm, electrical interactions are comparable to acoustic ones. With further increases in distance, weakly attenuated surface waves will dominate.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Achieving Near‐Ideal Subthreshold Swing in P‐Type WSe2 Field‐Effect Transistors

AbstractThe pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.

Gate-controlled spin injection polarity in 2D transistors with Schottky barrier

In 2D semiconductors, the Schottky barrier formed at the metal–semiconductor interface plays a crucial role in controlling electron and spin injection. To explore the spin injection mechanism under gate control, we study MoS2 coupled to ferromagnetic metals. We introduce a spin drift diffusion model which is applicable to the Schottky contact. In this system, the current passing through the Schottky barrier can be larger for the minority spin than for the majority spin due to the tunnel effect. We observe a polarity switching in spin injection with gate voltage variation when the conduction band bottom of the minority spin ferromagnetic metal is closely aligned with the Fermi level. Our results also suggest the spin injection efficiency can be tuned by gate control for half-metals.

Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation

Silicon-based spin qubits have emerged as promising candidates for scalable quantum information processing. This study first time investigates the behaviour of ultra-scaled 10 nm gate length and 3 nm channel thickness nanoscale double gate metal-oxide semiconductor field-effect transistors (MOSFETs) over a broad temperature range, from deep cryogenic (4 K) to room temperature (300 K). Employing the Non-Equilibrium Green’s Function (NEGF) method, the research explores the intertwined quantum and cryogenic behaviours of the various quantum phenomena, including eigen energies, eigen-functions, electron concentration, current characteristics, and more. This comprehensive analysis sheds light on the intricate interplay of quantum effects in nanoscale transistors under deep cryogenic conditions, offering valuable insights into the development of cryo-CMOS circuits for quantum computing.

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

This study examines the operational parameters of field-effect transistors (FETs) using single-gate (SG) and double-gate (DG) graphene nanoribbons (GNRs) within the analog/RF domain. A detailed exploration is conducted through an atomistic pz orbital model, derived from the Hamiltonian of graphene nanoribbons, employing the nonequilibrium Green’s function formalism (NEGF) for analysis. The atomic characteristics of the GNRFETs channel are accurately described by utilizing a tight-binding Hamiltonian with an atomistic pz orbital basis set. The primary focus of the analysis revolves around essential analog/RF parameters such as transconductance, transconductance generation factor (TGF), output resistance, early voltage, intrinsic gain, gate capacitance, cut-off frequency, and transit time. Furthermore, the study assesses the gain frequency product (GFP), transfer frequency product (TFP), and gain transfer frequency product (GTFP) to evaluate the balance between transistor efficiency, gain, and cut-off frequency. The research outcomes indicate that double-gate GNRFETs exhibit superior analog/RF performance in comparison to their single-gate counterparts. However, both types of devices demonstrate cut-off frequencies in the gigahertz range. The extensive data presented in this study provides valuable insights into the characteristics of SG and DG GNRFETs, particularly in terms of the figure-of-merit (FoM) for analog/RF performance, offering a comprehensive analysis of the trade-offs in analog applications. In addition, the analysis has been extended be performing a high-performance hybrid 6T static random-access memory (SRAM) to get the impact in their circuit level variation as well as improvement in their circuit performance.

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (I ON), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional I ON, I ON/I OFF ratio, and minimal sub-threshold swing (S) of ∼3.04 × 10−4 A μm−1, ∼1.2 × 1010, and ∼3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ∼0.75 mS/μm, ∼0.97 THz, and ∼102 GHz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ∼1.7 × 10−15 A μm−1 to 2.4 × 10−10 A μm−1 with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

Enhancing Carrier Mobility in Monolayer MoS2 Transistors with Process-Induced Strain.

Two-dimensional electronic materials are a promising candidate for beyond-silicon electronics due to their favorable size scaling of electronic performance. However, a major challenge is the heterogeneous integration of 2D materials with CMOS processes while maintaining their excellent properties. In particular, there is a knowledge gap in how thin film deposition and processes interact with 2D materials to alter their strain and doping, both of which have a drastic impact on device properties. In this study, we demonstrate how to utilize process-induced strain, a common technique extensively applied in the semiconductor industry, to enhance the carrier mobility in 2D material transistors. We systematically varied the tensile strain in monolayer MoS2 transistors by iteratively depositing thin layers of high-stress MgOx stressor. At each thickness, we combined Raman spectroscopy and transport measurements to unravel and correlate the changes in strain and doping within each transistor with their performance. The transistors displayed uniform strain distributions across their channels for tensile strains of up to 0.48 ± 0.05%, at 150 nm of stressor thickness. At higher thicknesses, mechanical instability occurred, leading to nonuniform strains. The transport characteristics systematically varied with strain, with enhancement in electron mobility at a rate of 130 ± 40% per % strain and enhancement of the channel saturation current density of 52 ± 20%. This work showcases how established CMOS technologies can be leveraged to tailor the transport in 2D transistors, accelerating the integration of 2D electronics into a future computing infrastructure.

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 °C using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high I on/I off ratio of 2.8 × 103 was realized by crystallization at 400 °C with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly-Ge TFTs for M3D applications.

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

This manuscript presents a pioneering study on enhancing analog and radio frequency performance through the implementation of negative capacitance source pocket double gate tunnel field-effect transistor. By integrating a ferroelectric material into the gate stack and introducing a fully depleted n-type pocket near the source/channel junction, we achieved significant enhancements in key metrics such as ON current (ION), switching ratio, subthreshold swing (SS), and various analog/RF parameters like transconductance (gm), cutoff frequency (fT) when compared to existing literature. Additionally, we extend our analysis to circuit-level applications such as inverter and 5-stage ring oscillator. Our findings reveal an impressive inverter delay of 1.09 ps with a gain of 104, as well as a ring oscillator operating at a frequency of 500 GHz. These results position the proposed device as an ideal candidate for high-speed, low-power applications.

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

AbstractDirect printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation

We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).