28nm Fully Depleted Silicon On Insulator Research Articles

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity.

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.

Reducing the nonlinearity and harmonic distortion in FD-SOI CMOS current-starved inverters and VCROs

This paper demonstrates experimentally how to reduce the nonlinearity of some analog and mixed-signal circuits by using the enhanced body effect provided by Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology. A current-starved CMOS inverter and a Voltage-Controlled Ring Oscillator (VCRO) are considered as case studies. The inverter is configured as a simple amplifier stage in which the harmonic distortion can be reduced and even removed by the combined action of the control voltages applied at the gate and bulk terminals of the current-source transistors. This current-starved inverter is used as the basic building block of a VCRO, where a more linear voltage-to-frequency characteristic can be achieved if the bulk terminal is used as the control voltage of the oscillator. The circuits under study have been designed and fabricated in a 28-nm FD-SOI technology and experimental results are shown to validate the presented approach.

TIARA: Industrial Platform for Monte Carlo Single-Event Simulations in Planar Bulk, FD-SOI, and FinFET

In this article, we present Tool suIte for rAdiation Reliability Assessment (TIARA), an industrial version of a Monte Carlo single-event simulation platform, enabling fast and accurate soft error rate (SER) estimations. This tool is capable of simulating logic cells manufactured in several technologies such as fully depleted silicon on insulator (FD-SOI), FinFET, and planar bulk CMOS. Moreover, TIARA is able to handle many different types of radiations including by-products of neutron or proton spallation, heavy ions and alpha particles, representative of terrestrial and space environments. Three use cases are shown in this article to illustrate TIARA capabilities. The first one compares the error rate in Geostationary Earth Orbit (GEO) orbit of all flip-flop variants from a 28-nm FD-SOI library. Second one evaluates multiple-cell upsets as a function of simulated array size for static random access memory (SRAM) cells manufactured in a 40-nm bulk technology. The last one shows alpha and neutron SER results for SRAM designed in a bulk-FinFET technology.

Radiation-Hardened Cortex-R4F System-on-Chip Prototype With Total Ionizing Dose Dynamic Compensation in 28-nm FD-SOI

This article presents a radiation-hardened Cortex-R4F system-on-chip prototype with integrated total ionizing dose (TID) dynamic compensation capabilities, designed and fabricated in 28-nm fully depleted silicon-on-insulator (FD-SOI) technology. The processor was made robust to single-event effects, thanks to several design techniques: error correcting code (ECC) protected and bit-interleaved memories, optimized radiation-hardened sequential cells, and sensitive logic cells filtering. To counter the TID effects on the processor functionality and performances, the system embeds an integrated digital dosimeter. The dosimeter is capable of computing the TID in real time and providing the information to the system. Using a software lookup table (LUT), coupled with 28-nm FD-SOI technology support of asymmetric and wide-body-biasing, the reported TID can be converted to a request made to an external body-bias generator and be fully compensated. The system, operating at 0.9 V and 500 MHz, was tested under space grade radiations and has shown no failure in the 0 krad(Si) to 50 krad(Si) TID range.

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

Preventing device obsolescence in Internet-of-things (IoT) is mandatory for its massive deployment to be ecologically sustainable. This calls for ultralow-power (ULP) reprogrammable microcontroller units (MCUs) for long lifetime, yet with sufficient computing performance to extract the meaningful information from the sensed data before transmitting it to the cloud. In this article, we present the SleepRunner MCU with logic/memory/power management co-optimization for best exploitation of the forward back biasing (FBB) capability in fully-depleted silicon-on-insulator (FDSOI) technologies. For low active power, we use ultralow-voltage (ULV) low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> logic with upsized gate length and asymmetric FBB, a ULP SRAM macro with low read-access energy and switched-capacitor voltage regulators (SCVRs) for ULV supply generation from a single I/O voltage. The custom ULP SRAM macro is based on an ultralow-leakage (ULL) FBB-compatible bitcell for low SRAM retention power. In addition, a dual-loop digital unified frequency/back-bias regulation (UFBR) system efficiently compensates process and temperature variations with short wakeup from the zero-back-bias deep-sleep mode. Performance is measured for a synthetic benchmark and biomedical inference applications. The measured 40-MHz 2.6- μW/DMIPS (3.3 μW/MHz) active and 131-nW/kB deep-sleep power consumptions with CPU state retention are respectively 3 × and 2.5 × lower than for a conventional MCU design in this technology. This demonstrates the interest of 28-nm FDSOI with the proposed FBB-driven system optimization for ULP MCUs.

Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits – Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs

This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks – such as switches, simple-stage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based $\Sigma \Delta $ modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.

High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

Heuristic Methods for Fine-Grain Exploitation of FDSOI

Fully depleted silicon on insulator (FDSOI) is attractive for its low cost and low power; the mixed-Vt and body-bias levers that it affords expand the performance-power solution space. However, in FDSOI, different-Vt (i.e., low Vt and regular Vt) devices must be isolated from each other, which makes realization of fine-grained mixed-Vt/body-biasing in layout extremely challenging. In this article, we study heuristic methods aimed at exploitation of fine-grained mixed-Vt in FDSOI implementation. We propose a novel speed domain partitioning (SDP) problem formulation that comprehends the spatial contiguity restrictions arising from flip-well structure of low Vt regions in popular 28-nm commercial FDSOI offerings. We explore a wide space of implementation flows that include an integer linear programming (ILP)-based approach, and a heuristic (sensitivity-based) optimization. Our experimental studies have been performed across multiple commercial enablements. We observe that outcomes are library- and design-dependent. For implementations using generic library options, up to 20% speed improvement with 54% low Vt region is seen for one out of four testcases studied. For implementations using “rich” library options, up to 7% speed improvement with 26% low Vt region is achieved. We provide a discussion that summarizes root-cause, intrinsic difficulties of fine-grained exploitation of mixed-Vt. Finally, we suggest a “decision tree” to help assess a design’s amenability to fine-grained mixed-Vt implementation, and to help guide design flow selection for better design QoR.

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI

Bias temperature instability (BTI) degradation poses increasingly critical lifetime reliability design challenges in static random access memory (SRAM), as fabrication technology marches toward a very deep nanometer regime. This paper presents circuit techniques that enable on-chip dynamic reliability management, which intelligently monitors and mitigates the half-selected cell stability failure due to BTI degradation in SRAM. The dynamic reliability management is achieved through the automated BTI-aware write word-line (WWL) control, whereby it detects the BTI degradation in SRAM cells through a replica row-based BTI-aware stability monitor and adjusts the WWL voltage level with two-phase write operation (TPWO). The WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Silicon validation of a 16-kb SRAM based on a 28-nm fully depleted silicon on insulator (FDSOI) technology successfully demonstrates that the half-selected cell stability failure is eliminated from 57.13% down to 0% with the proposed approach at a marginal 3.42% power and 10% area overheads.

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

Total Ionizing Dose Effect on Ring Oscillator Frequency in 28-nm FD-SOI Technology

The total ionizing dose (TID) is a mechanism that threatens the reliability of transistors under radiation. In the literature, we found contradictory TID experimental results between device and circuit studies of fully depleted silicon-on-insulator (FD-SOI) technology. To resolve that conflict, we designed a special ring oscillator (RO) circuit in which the n-FET and p-FET gate-potentials can be programmed. The RO circuits were fabricated using 65-nm bulk-CMOS and 28-nm FD-SOI foundry baseline technologies and were dosed with 60Co gamma radiation up to 200 krad (SiO2). In addition, we measured drive current variations in the 28-nm FD-SOI after irradiation. Traditionally, there has been a belief that the TID of n-FETs is more dominant than that of p-FETs. However, we found that in FD-SOI, the TID effect of p-FET governs circuit performance degradation.

A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology for UWB applications

In millimeter wave systems, performance degradation mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for ultra-wide band applications identified for possible 5G usage. For this purpose, a novel differential symmetrical load delay cell based 3-stage ring oscillator has been introduced to design the ring-VCO. The 28 nm CMOS Fully Depleted Silicon On Insulator (FDSOI) technology is adopted for designing this VCO circuit with 1 V power supply while a new voltage control through the transistor body bias is implemented. The simulated results show that the proposed oscillator works in the tuning range of 29–49 GHz and dissipates 3.75 mW of power. It exhibits a phase noise of −129.2 dBc/Hz at 1 MHz offset from 49 GHz oscillation frequency, and a remarkable Figure of Merit (FoM) of −217.26 dBc/Hz. With similar power supply, the phase noise rises to −93.16 dBc/Hz for a second oscillator involving more of active components exactly 9 delay cells. Further, the impact of the operation temperature variation on the VCO performance is investigated. Results show a drift in the oscillation frequency for a temperature step from 27 °C to 40 °C and a degradation of 3dBc in the phase noise performance.

Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.

Accurate Resolution of Time-Dependent and Circuit-Coupled Charge Transport Equations: 1-D Case Applied to 28-nm FD-SOI Devices

We present a new model for simulation of single-event effects in fully depleted silicon on insulator (FD-SOI) technology. The model is based on direct resolution of the drift-diffusion equations on a 1-D grid aligned with the source–channel–drain axis of the impacted MOSFETs. Our model is dynamically interfaced with a SPICE solver and shown to be both computationally efficient and in good correlation with 3-D technology computer-aided design (TCAD) radiation simulations. This allows us to embed the module in our soft-error rate simulation platform, enabling projections on logic cells in 28-nm FD-SOI.

Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance degradation typical of low-voltage operations. In this paper, we demonstrate the capabilities of the PULP (Parallel Ultra-Low Power) platform on an algorithm for seizure detection, representative of a wide range of EEG signal processing applications. Starting from the 28-nm FD-SOI (Fully Depleted Silicon On Insulator) technology implementation of the third embodiment of the PULP architecture, we analyze the energy-efficient implementation of the seizure detection algorithm on PULP. The proposed parallel implementation exploits the dynamic voltage and frequency scaling capabilities, as well as the embedded power knobs of the PULP platform, reducing energy consumption for a seizure detection by up to 10× with respect to a sequential implementation at the nominal supply voltage and by 4.2× with respect to a sequential implementation with voltage scaling. Moreover, we analyze the trans-precision optimization of the algorithm on PULP, by means of a hybrid fixed- and floating-point implementation. This approach reduces the energy consumption by up to 43% with respect to the plain fixed-point and floating-point implementations, leveraging the requirements in terms of the precision of the kernels composing the processing chain to improve energy efficiency. Thanks to the proposed architecture and system-level approach for optimization, we demonstrate that PULP reduces energy consumption by up to 140× with respect to commercial low-power microcontrollers, being able to satisfy the real-time constraints typical of bio-medical applications, breaking the barrier of microwatts for a 50-ms complete seizure detection and a few milliwatts for a 5-ms detection latency on a fully-programmable architecture.

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings.

UTBB FDSOI: Evolution and opportunities

As today’s 28nm FDSOI (Fully Depleted Silicon On Insulator) technology is at the industrialization level, this paper aims to summarize the key advantages allowed by the thin BOX (Buried Oxide) of the FDSOI, through the technology evolution but also new opportunities, among logic applications and extending the possibilities offered by the platform. We will summarize how the advantages provided by the thin BOX have been first explored and developed, and how the back biasing techniques are the key to the outstanding performances provided by the FDSOI at low voltage. Then, as the FDSOI technology is also a solution to develop innovative platforms and applications, we will detail some opportunities. In particular, we will present monolithic 3D integration, ultra-low power devices for IoT (Internet of Things) and ultra-sensitive sensors.

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

In this paper, we propose to study the impact of 28nm FDSOI technology on energy study. In fact, due to the effects of the Moore’s law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On-Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.