14nm FinFET Research Articles

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105mW at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b at a supply voltage of 0.8 V. The VD, implemented in an experimental chip fabricated in 14-nm CMOS FINFET, exploits set-partitioning principles and embedded per-survivor decision feedback to reduce implementation complexity and power consumption. The active area of the VD with 12 slices, each operating at one-eighth of the modulation rate, is $0.507\times0.717$ mm2. Experimental results showing system performance are obtained by using a (215–1)-bit pseudo-random binary sequence. The impact of the synchronization length and survivor path memory length on the detector design and system performance are shown. A new pipelined reduced-state sequence detector algorithm is presented for high-speed implementations. A novel speculative symbol timing recovery scheme is proposed. New simulation results are obtained to compare the performance of the Reed–Solomon (RS)-encoded 4-PAM scheme with that of the concatenated RS 4-D 5-PAM trellis-coded-modulation (TCM) scheme over an ideal band-limited additive-white-Gaussian-noise channel. Drawing on the results achieved for the VD, novel design techniques for a high-speed low-complexity eight-state 4-D 5-PAM TCM decoder is proposed.

Application and Product-Volume-Specific Customization of BEOL Metal Pitch

High-volume manufacturing of integrated circuits is what drives the semiconductor industry and the scaling of CMOS; however, shrinking all feature sizes is not optimal for all product volumes and applications. While scaling transistors provide improvement in performance at power in general, concerted scaling of the back-end-of-line (BEOL) interconnects provides improvement in density but at some expense of performance and quality. In this paper, we explore the benefits of relaxing the BEOL metal pitches as a tunable knob for application-specific optimization as a function of product volume. This paper demonstrates that a relaxed BEOL (r-BEOL) methodology can be applied at block level as well as chip level to provide performance and quality benefits while considering density constraints. The benefits of an r-BEOL pitch for power, timing, design for manufacturability, routing congestion, and signal integrity are considered for a 16-nm FinFET technology. Silicon results using relaxed M4–M7 metal layers are used to validate the simulation comparisons.

A $4\times45$ Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation

This paper presents a high-swing vertical-cavity surface-emitting laser (VCSEL) driver with two-tap feed-forward equalizer (FFE) in 14-nm FinFET CMOS technology. The design features a standby mode with power-ON time below 10 ns and 86% of power saving. Based on system-level simulations, the impact of the driver swing, tap delay, and weight on the optical eye-opening is studied and it is shown that the FFE combined with high-swing driving can improve the output eye at rates beyond two times the bandwidth of the VCSEL. By applying an extra supply, the output stage is optimized to provide high swing (0.65 V) without suffering from the slow response of a transistor in the triode region. In addition, the bias and modulation currents can be adjusted to accommodate different VCSELs. The designed circuit is tested with two VCSEL types. It is bonded to common-cathode 20 and 18 GHz VCSELs, and in both the cases, data transmission at 45 Gb/s with bit error rate lower than 10−12 is measured. The total power dissipation is below 100 mW, providing a power efficiency of better than 2.11 pJ/bit. To the best of our knowledge, this design is the fastest VCSEL driver in any CMOS technology, which is also capable of burst mode operation.

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.

A 180 mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT Using Self-Biasing Deep N-Well in 16-nm CMOS FinFET

We introduce the first monolithic step-up dc–dc converter operating at deep sub-1 V (i.e., 0.18–0.4 V) that outputs significant power for Internet-of-Things with a peak power efficiency of 81.2% at 50 $ {\mu }\text{W}$ output power for the 0.18-V input and 87.1% at 300 $ {\mu }\text{W}$ output power for 0.4 V. It is implemented in 16-nm FinFET CMOS and uses an MOS transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter verifies the dc–dc output quality.

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors.

Technology Scaling Trend of Soft Error Rate in Flip-Flops in &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$1\times$ &lt;/tex-math&gt; &lt;/inline-formula&gt; nm Bulk FinFET Technology

This paper presents the soft error rate (SER) in flip-flops of 10-nm FinFET technology, and discusses the scaling trend of SER from 14- to 10-nm FinFET technologies. Alpha and neutron irradiation test results show huge SER improvement in 10-nm FinFET technology. In a 10-nm FinFET, the alpha-induced SER decreases by $13.4\times $ , and the neutron-induced SER decreases by $3.1\times $ , compared to the 14-nm FinFET technology. The SER improvement is analyzed with the physics-based 3-D technology computer-aided design and Monte Carlo simulations. The simulation results show that fin-width scaling reduces the charge generation as well as charge collection which explains the SER improvement observed in 10-nm FinFET technology.

Investigations on performance metrics of FINFET based 8- bit low power adder architectures implemented using various logic styles http://www.indjst.org/index.php/indjst/article/view/111071 1489988072

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42µW to 882.6µW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001µW to 945.76µW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7µW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9µW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344µs to 0.46µs. The delay of Fin FET architecture ranges from 0.19µs to 0.28µs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers. Keywords: Complementary Pass-transistor Logic, Gate Diffusion Input, Low Power Adder, Transmission Gate, CMOS, FINFET

802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS

This paper presents an 802.11g/n compliant wake-up radio solution that consists of an innovative on–off keying (OOK) emulating orthogonal frequency division multiplexing (OFDM) modulation scheme, and a fully integrated, highly scaled, ultra-low power wake-up receiver design in 14-nm FinFET CMOS technology requiring only a 32-kHz real-time clock reference. The receiver achieves −72-dBm sensitivity and +20 dBr adjacent channel interference (ACI) rejection at 10−3 bit error rate (BER) while consuming $95~\mu \text{W}$ . This receiver can be utilized along with any legacy Wi-Fi transmitter without changing any hardware.

Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit $\Delta\Sigma$ RF-DAC in 16-nm FinFET

This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin.

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.

40-Gbit/s 850-nm VCSEL-Based Full-CMOS Optical Link With Power-Data Rate Adaptivity

An optical link based on directly modulated vertical-cavity surface-emitting laser (VCSEL) at 850-nm wavelength using commercial VCSEL and photodiode operating error-free BER < 10−12) at 40 Gbit/s is reported. The transmitter is implemented in a 14-nm FinFET CMOS while the receiver (RX) in 28-nm digital bulk-CMOS technologies. This is the fastest 850-nm VCSEL-based single-lane non-return-to-zero optical link with all the analog front-end components fabricated in CMOS. An energy-per-bit of 3.4 pJ/bit is measured at 40 Gbit/s. At lower data rates, the bandwidths of the circuits can be decreased adaptively to save power. This results in 2.7 pJ/bit at 20 Gbit/s. A sensitivity of −1.9 dBm optical modulation amplitude could be measured at the RX for 40 Gbit/s.

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation

A novel high-speed and highly reliable sense-amplifier-based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage ( $V_{\mathrm {DD}}$ ) operation. The SAFF-TCD adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus overcoming the operational yield degradation, current contention, and glitches of previous SAFFs. The operational yield, speed, hold time, energy consumption, and area of the proposed and previous FFs are quantitatively compared for a wide range of $V_{\mathrm {DD}}$ with 22-nm FinFET technology. It is shown that the minimum $V_{\mathrm {DD}}$ of the SAFF-TCD is 573 mV lower than that of previous SAFFs, which means the SAFF-TCD can operate even when $V_{\mathrm {DD}}$ is in the near-threshold or subthreshold region. At 0.3–0.4 V, the SAFF-TCD operates twice as fast as the master–slave-based FF (MSFF) with a practical hold time. Even with these benefits, the energy consumption overhead is limited to less than 20% compared with that of MSFF, and the area is similar to that of previous SAFFs.

Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs

In current CMOS technology, parameter variations are playing a vital role in limiting the benefits of downscaling, especially in the nanodomain. This work presents the investigation of random dopant fluctuation (RDF) in several possible line-edge roughness (LER)-induced fin shapes of spacer- (i.e., correlated LER) and resist- (i.e., uncorrelated LER) defined patterning techniques for a 14-nm FinFET structure. The three-dimensional (3-D) technology computer-aided design simulation on a large statistical ensemble has been carried out to analyze the impact of the RDF on various device parameters such as threshold voltage, drive current, off current, and drain-induced barrier lowering. It is observed that the impact of RDF on electrical parameters mainly depends on the fin shape and is dominant in all resist-defined FinFET structures. It is also found that the impact of RDF can diminish significantly using the spacer-defined patterning technique. Further, the impact of RDF in spacer- and resist-defined FinFET structures has been investigated for noise margins of 6-T static random access memories (SRAM). It is concluded that random dopant variations in SRAM performance offer better immunity in the case of spacer-defined FinFETs compared with resist-defined FinFETs.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference ( $\Delta V_{\textrm {DIF}}$ ) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of <30% that is margined in while programming, by employing a sense margining logic in the SA. Scalability of CTT has been established by the first demonstration of CTT-based MTPM in 14-nm bulk FinFET technology with read cycle time of 40 ns at 0.7-V VDD.

A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS

An automatically placed-and-routed all-digital PLL for high-performance clock generation and distribution in many-core processors is presented. The proposed design leverages a phase domain architecture, and features an embedded TDC constructed from standard cells. TDC resolution is enhanced through the use of a phase interpolator. The standard cell library is extended with custom oscillator cells are designed to achieve optimized power, performance, and area. Timing and handling of potentially metastable paths is additionally handled by the digital design flow. The clock generator has been fabricated in a 14-nm FinFET process, and occupies an area of 0.009 mm2. The design features a tuning range from 1.0 to 5.5 GHz (80%). Output period jitter of 1.29 ps is achieved with a power consumption of 9.7 mW.

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on ${I}$ – ${V}$ characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger $\sigma {V}_{T}$ than that from the LER and the RDs, respectively. However, the variability induced threshold voltage ( ${V}_{T}$ ) shift is minimal for the MGG (around 2 mV), but ${V}_{T}$ shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in ${V}_{T}$ and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation.

A robust and low-power near-threshold SRAM in 10-nm FinFET technology

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.

Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20nm System on Chip (SoC), 16nm FinFET (16FF) and 10nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.