In this brief, a novel design methodology for Doherty power amplifier (DPA) MMIC is proposed to improve the efficiency of the DPAs. The design equations of a compact harmonic-controlled bias network (CHCBN) are derived, which can achieve inverse class-F amplifier load conditions with adjustable fundamental frequency impedance, this approach effectively improves the saturated and back-off efficiency of the DPA. An active second harmonic injection network (HIN) is proposed which utilizes the second harmonic components generated by the carrier and peaking devices for mutual injection to achieve the amplitude modulation of the DPA drain waveform in the saturated state, further improving the saturated efficiency of the DPA. To validate the methodology, a C-band high efficiency DPA MMIC is designed and fabricated in a 0.25 μm GaN-HEMT process. The measurement results show that the fabricated DPA exhibits the saturated output power (Psat) of 39.6 dBm–40.6 dBm, with a saturated drain efficiency (DE) of 53.9%–61.5%, and a 6-dB back-off DE of 51.4%–56.0% over the 4.8-5.4 GHz frequency band. The proposed DPA demonstrates the highest 6-dB back-off efficiency among the published broadband GaN MMIC DPAs operating in similar frequency band.

Charge sensitive amplifiers (CSA) are key elements for the readout of charge signals produced by ionizing radiation and particle detectors. In nuclear microelectronics, these circuits are characterized by stringent requirements in terms of equivalent noise charge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(ENC)</i>, and maximum input charge specification, which is tied to the voltage output swing capability of the amplifier itself. The need for periodic or continuous discharge of the feedback capacitance further constrains the design choices. In this work, a circuital solution that acts on the feedback discharge path to optimize the quiescent operating point of the CSA is presented, allowing an increase in the effective dynamic range of the CSA without affecting the spectroscopic resolution of the system. In addition, the proposed reset architecture allows to use a single power supply, avoiding the double supply generally used to increase the dynamic range, gaining in system compactness. Experimental measurements show an increase of +107% in the dynamic range with respect to standard reset architectures of state-of-the-art CSAs for low-capacitance (≤ 0.1 pF) semiconductor radiation detectors, achieving a total maximum input charge of ≃3×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> el. (47 fC), corresponding to 1.08 MeV equivalent energy in silicon or 1.31 MeV in cadmium-zinc-telluride detectors. The preamplifier implements a fast feedback capacitance discharge rate of 2.5 fC/ns (t<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">90−10</sup> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">_fall</i> =18.8 ns over the full output range), and preserves an excellent intrinsic noise performance of 3.7 electrons rms, making it suitable for high-speed, high-energy-resolution spectroscopy applications.

Ferroelectric-capacitor-based memory (FeRAM) is a promising emerging non-volatile memory technology that offers fast access and high endurance. Recent studies have demonstrated Ferroelectric-capacitor-based memory (FeRAM) has the potential to support Non-Destructive Readout (NDRO) as well as 3D stacking, enabling read operations that do not disturb or minor disturb the stored polarization state and higher density. However, variations in ferroelectric materials and layer structures lead to diverse hysteresis behaviors, resulting in different sensing requirements. In addition, the reduced capacitor size in deeply stacked 3D architectures further decreases the available charge, making accurate readout increasingly challenging. To better understand these issues, this work presents a highly scalable direct-capacitance-conversion characterization circuit that is capable of extracting the equivalent ferroelectric capacitance from a 3D FeRAM array. Leveraging a continuous-time delta-sigma modulator (CTDSM), the proposed platform can accurately quantize small ferroelectric equivalent capacitances ranging from 0 to 72fF with low noise and high resolution, and achieves a capacitance resolution of 0.045fF<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> while consuming only 3μW power and occupying 0.001mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area under a 22nm FDSOI technology. These results demonstrate the capability to characterize 3D FeRAM arrays with up to 64 vertically stacked ferroelectric capacitors (FeCAPs) and highlight strong scalability for large-scale FeRAM evaluation and design exploration.

Pre-sampling multiplying digital-to-analog converters (MDACs) feature high speed and energy efficiency. However, the parasitic capacitance between the sampling capacitor and the reference capacitor in the pre-sampling MDAC can induce gain and intercept errors in the pipeline stage, which significantly degrades the linearity of the entire pipelined ADC. This work presents a pre-sampling MDAC with parasitic compensation using a split-capacitor technique in the analog domain, combined with an intercept calibration method to correct the gain and intercept errors. Employing this technique, a 12-bit pre-sampling pipelined ADC fabricated in a 28nm CMOS process consumes 495mW at a 10GS/s sampling rate, achieving a signal-to-noise-and-distortion ratio (SNDR) of 50.8dB and a spurious-free dynamic range (SFDR) of 60.7dB with a Nyquist input signal.

Charge-discharge capacitive sensing circuit has the advantages of high precision, simple structure and low power consumption. However, its low-frequency noise performance is limited by the fluctuations of the forward voltage of the switching diodes in the ring-diode circuit. In this brief, a chopper stabilization circuit is designed by periodically interchanging the positions of the four diodes to suppress the low-frequency noise introduced by the ring-diode circuit. The principle is analyzed and the noise performance is validated. Experimental results show that this method can significantly suppress the low-frequency noise of the sensing circuit. At a carrier frequency of 2.5 MHz, the equivalent capacitance resolution of the sensing circuit at 0.01 Hz is improved from about 1.1 aF/Hz<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> to about 0.12 aF/Hz<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup>. The optimized sensing circuit can promote the application in fields with high requirements for low-frequency performance, such as space inertial sensors and planetary seismometers.