Today, lasers are unavoidable in the wide range of technologies that are used in different areas such as industry and medicine, which illustrates the strong synergic relationship between basic physics and its practical application. Here, our focus of interest is laser-induced optical breakdown in the solid materials that becomes important in a wide range of industrial applications with the development of femtosecond lasers. It is shown that the effects of the laser-induced optical breakdown in solid media can be useful, but also can lead to the modification of the material’s properties and material damages. Because of that, control of this process is crucial for laser applications. In order to achieve this, it is necessary to form a theoretical model in the sense of understanding of all relevant processes and dependence on the laser’s parameters as well. We used the rate equation model to follow the process’s dynamics. We demonstrated that the laser wavelength significantly influences the outcome of the mechanisms of interest, and therefore laser induced breakdown.

This paper presents a novel reliability life test bench designed especially for lifetime tests under pulse conditions on high RF power devices. Investigations are conducted into the monitoring of RF power, drain, gate, and current voltages and currents under varied temperature and pulse conditions. On a specialized RF S-band test bench, a 3000-hour pulsed radiofrequency life test has been carried out in operational modes. Following these accelerated ageing tests, the data treatment yielded investigation findings regarding degradations of critical electrical parameters, which are presented. In order to stress the Lateral-Diffused Metal Oxide Semiconductor (LDMOS), many duty cycles are applied. It demonstrates that hot carriers-generated interface states (traps) and trapped carriers are related to the dominant degradation phenomenon through tracking of a set of RF parameters (Pout, Gain, and Drain Efficiency: DE).

We present a two-stage lattice Monte Carlo method for predicting atomic ordering, surface segregation, and cavity healing in hollow Au–Ag nanocages. Starting from face-centered cubic (fcc) and icosahedral templates (4500 sites), we construct 3000-atom cages with Au:Ag ratios of 1:1, 1:3, and 3:1. We propose a modification to the Warren–Cowley short-range order parameter, in which atomic concentrations are calculated locally, taking into account atomic coordination numbers. This makes it applicable to nanoparticles with pronounced surface segregation. Our results indicate that Ag preferentially enriches outer layers and vertices, while Au tends to occupy subsurface sites, lowering energy by 5–10 meV/atom relative to random alloys. In systems with a high Au:Ag ratio, the inner layers are nearly free of Ag, while systems with a low Au:Ag ratio have the maximum number of mixed Ag–Au bonds and a more uniform local order. Our computational pipeline—capable of performing millions of Monte Carlo moves per minute—can be extended to multicomponent systems and off-lattice potentials for rapid nanocage design.

In this paper, a true random number generator (TRNG) architecture is developed by utilizing different entropy sources such as Thermal noise, Metastability, and Timing Jitter. Thermal noise is generated by connecting the base and collector terminal of two BC547 transistors, timing Jitter is generated by using the All-Digital Phase Locked Loop (ADPLL), and Metastability is generated by using a DFF. The thermal noise source uses IC741 OPAMP-based amplifier and comparator circuits to obtain digital data, and it is developed on a separate breadboard. Metastability and timing Jitter sources were developed using an Artix 7 FPGA to obtain digital data. XOR operations were performed on digital data obtained from thermal noise and Metastability and timing Jitter sources to obtain random bitstream. Pure random bitstreams consisting of more than 24000 bits were generated by performing sampling using a DFF. Analog Discovery was used to provide an input source for the amplifier circuit and to show the output waveform of the comparator circuit. Tera Term was used to display bitstream on the monitor using a UART transmitter. The proposed TRNG utilizes 147 LUTs and 106FFs and achieves a throughput value of 299.13 Mbps.

This paper presents a design methodology for a 2.6 GHz CMOS LC Voltage-Controlled Oscillator (VCO) using the AMS 0.35 μm CMOS process. The approach focuses on minimizing power consumption, reducing phase noise, and maximizing the figure-of-merit (FOM). To overcome the complex trade-offs in analog design, a metaheuristic Particle Swarm Optimization (PSO) algorithm is employed to determine the optimal dimensions of the MOS transistors. The PSO targets the reduction of phase noise while respecting technological and performance constraints. The proposed VCO is simulated using ADS, showing a phase noise of –125.35 dBc/Hz at 1 MHz offset and a power consumption of 9 mW. A comparative study with existing designs highlights the advantages of the proposed method, demonstrating improved performance in terms of phase noise and FOM. These results confirm the effectiveness of the optimization-based design approach for high-performance RF VCOs in CMOS technology.

This research study aims to understand the variation of power dissipation according to the variation of power clock provided to Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, 2N-N-2P, and 2N-2N-2P Adiabatic logic families. This study aims to understand how varying the parameters of the power clock affects the adiabatic circuit’s power consumption and the output signal integrity. The paper considers the NAND gate as a bench-marking circuit to gather data for this study by implementing it in the considered logic families. The input power clock’s frequency ranges from 100 MHz to 1 GHz. This study is particular to the scenario of Ultra Low Supply Voltage of the power clock hence the decided range for analysis of the voltage is 0.3V ≤ Vdd ≤ 0.6V and industrially popular 1V. The final result sums up the performance of all 4 adiabatic logic families considered above and identifies Positive Feedback Adiabatic Logic as the most power-saving family overall and 2N-N-2P Adiabatic Family as the most immune to frequency variation. The general trend is also observed to be disrupted for 0.3V and 0.4V as 2N-N-2P unexpectedly consumes less power than 2N-2N-2P. A similar change of trend in 0.5 and 0.6, where Efficient charge Recovery Logic performs better than 2N-N-2P and 2N-2N-2P, and in 1V, it outperforms all other techniques.

This paper presents an improved solar-powered street light. It consists of a microcontroller, DC-DC power converter, a Light-emitting diode (LED), sensors, and other components coupled together. So, this system charges during the day when the Light-dependent resistor (LDR) attached to the solar panels detects sunlight and begins charging the battery. This voltage is, of course, high and is stepped down using a DC-DC power buck converter, which reduces the voltage to about 15 volts. The bucked-down voltage is used to charge the battery until the battery is full. The light switches ON at night when the LDR can no longer detect sunlight. When this happens, signals are sent to the microcontroller, which now sends other signals through a transistor switching on the LED. When switched ON, the lights at dim and remain so unless an object or person approaches, which it then senses by the motion sensor, and the light intensity is then increased till the passing person or object is out of range. One distinguishing characteristic of this research work is that it captures all the images of the moving objects that pass across the area coverage area and store them for security and analytical purposes, unlike the conventional ones.

This study aims to develop and analyze facial recognition patterns, a biometric-based approach to identify individuals through facial features. Such biometric patterns can be used as a tool to verify the presence of a student. Face recognition technology utilizing Raspberry Pi to assess the appropriateness of biometric patterns. The facial matching process is employed to ascertain student attendance in class. The Principal Component Analysis (PCA) technique is employed in the face detection procedure. The sample testing was carried out on a group of fifty students, with each student supplying thirty different facial photos. 1,500 images were processed utilizing the PCA algorithm within the OpenCV library. A 95% accuracy rate was achieved with the photos that were obtained, which have a resolution of 640x480 pixels.

Due to improved efficiency and lower greenhouse gas emissions, electric motors, also known as traction motors, are gradually replacing internal combustion engines (ICEs). Batteries and ultra-capacitors provide all or some of the electrical energy needed for the electric vehicle (EV) to run. In a plug-in or hybrid electric automobile, the internal combustion engine provides the charging energy for the battery or ultra-capacitor. At the same time, the AC supply connected to the grid line does the same. Regenerative braking is how the electric motor charges the battery. The plug-in electric automobile returns the energy from the battery or ultra-capacitor to the AC grid. The conversion process between an electric motor and the grid, and vice versa, requires power electronic converters (PECs). This study clarifies the purpose of PECs in EVs. EV power conversion relies heavily on the bidirectional DC-DC converter. Present are comprehensive analysis, comparison, and implementation of contemporary bidirectional DC-DC converter topologies. The analysis is done on improving PECs to increase the vehicle system's dependability and efficiency.

This paper introduces two new hardware architectures for the temperature control of a heating element. The first system uses a digital thermometer, the NodeMCU ESP8266 development kit, a graphic OLED display module, and a heating resistor. The monitored data can be displayed on the graphic screen and wirelessly transferred to several Internet of Things (IoT) platforms, including Blynk, Ubidots, and Cayenne MyDevices. The second design is based on an Arduino Nano and employs an NTC thermistor as a temperature sensor, an RF transceiver module for data transmission, and an LCD screen to show the temperature of the heating element. Both systems were validated through temperature control tests using PID and fuzzy logic controllers. Performance was assessed based on various criteria, such as integral of absolute error (IAE), integral of time absolute error (ITAE), and integral of square error (ISE).