Abstract Spiking Neural Networks (SNN) are biologically inspired Artificial Neural Networks (ANN) that emulate the behaviour of biological neurons in spiking-based computational units. However, machine learning (ML) models are known to be vulnerable to adversarial noise, and particularly to universal adversarial perturbations (UAP) and adversarial patch (AP) attacks. Despite the claimed inherent robustness of SNNs to adversarial noise, attacks with UAP and AP remain under-explored in the spiking domain.
This paper revisits the adversarial noise generation method from its first principles. Specifically, we consider a realistic spiking-aware setting that takes into account constraints from the neuromorphic domain, such as event sparsity and spike-timing integrity. We introduce our approach for creating Spiking-compatible adversarial attacks and a spiking UAP and AP destined for event-based computer vision systems.
We propose a novel, efficient spike-based adversarial noise generation approach that respects neuromorphic constraints and show that SNNs can be the victims of more tangible and realistic types of attack.

Abstract This paper extends prior work on the computational power and complexity of spiking neural networks (SNNs) by introducing a refined theoretical framework. We present three models for neuromorphic computation — spike-input, pre-processing, and interactive — and formalise how these models relate to complexity classes defined by time, space, and energy constraints. We show that spike waves can be reduced to singleton spike trains with only linear overhead and establish structural results connecting spiking machines to Boolean circuits and non-uniform complexity classes. The paper concludes with completeness results for neuromorphic complexity classes and outlines open problems regarding energy complexity and resource trade-offs.

Abstract DNA and other biopolymers are being investigated as new computing substrates and alternative to silicon-based digital computers. However, the established top-down design of biomolecular interaction networks remains challenging and does not fully exploit biomolecular self-assembly capabilities. Outside the field of computation, directed evolution has been used as a tool for goal directed optimization of DNA sequences. Here, we propose integrating directed evolution with DNA-based reservoir computing to enable in-material optimization and adaptation. Simulations of colloidal bead networks connected via DNA strands demonstrate a physical reservoir capable of non-linear time-series prediction tasks, including Volterra series and Mackey–Glass chaotic dynamics. Reservoir computing performance, quantified by normalized mean squared error (NMSE), strongly depends on network topology, suggesting task-specific optimal network configurations. Implementing genetic algorithms to evolve DNA-encoded network connectivity effectively identified well-performing reservoir networks. Directed evolution improved reservoir performance across multiple tasks, outperforming random network selection. Remarkably, sequential training on distinct tasks resulted in reservoir populations maintaining performance on prior tasks. Our findings indicate that DNA-bead networks offer sufficient complexity for reservoir computing, and that directed evolution robustly optimizes performance.

Abstract Spiking neural networks (SNNs) provide an efficient framework for processing dynamic spatio-temporal signals and for investigating the learning principles underlying biological neural systems. A key challenge in training SNNs is to solve both spatial and temporal credit assignment. The dominant approach for training SNNs is backpropagation through time (BPTT) with surrogate gradients. However, BPTT is in stark contrast with the spatial and temporal locality observed in biological neural systems, and leads to high computational and memory demands, limiting efficient training strategies and on-device learning. Although existing local learning rules achieve local temporal credit assignment by leveraging eligibility traces, they fail to address the spatial credit assignment without resorting to auxiliary layer-wise matrices, which increase memory overhead and hinder scalability, especially on embedded devices. In this work, we propose traces propagation (TP), a forward-only, memory-efficient, scalable, and fully local learning rule that combines eligibility traces with a layer-wise contrastive loss without requiring auxiliary layer-wise matrices. TP outperforms other fully local learning rules on N-MNIST and SHD datasets. On more complex datasets such as DVS-GESTURE and DVS-CIFAR10, TP showcases competitive performance and scales effectively to deeper SNN architectures such as VGG-9, while providing favorable memory scaling compared to prior fully local scalable rules, for datasets with a significant number of classes. Finally, we show that TP is well suited for practical fine-tuning tasks, such as keyword spotting on the Google speech commands dataset, thus paving the way for efficient learning at the edge.

Abstract Intracortical Brain Computer Interfaces (iBCIs) hold the potential to revolutionize neurotherapeutics, but they must overcome technological challenges such as the high data rates generated by high-channel-count neural sensors and the stringent power and volume constraints of implantable devices. In addition, the brain-wide coverage needed for a deeper understanding of brain processes challenges the synchronization between distributed neural sensors and the central neural hub. To address these challenges, we present a deterministic-latency and power-efficient serializer-deserializer (SerDes) telemetry network that effectively mitigates the synchronization issue under strict power and volume constraints. The serializer on the sensor side employs event-based sampling and a packet-based address-event representation (AER) transmission protocol, achieving a low power consumption of only 127 µW and a low latency variation < 10 µs. A crystal-free clock source is employed on the sensor side to minimize power consumption, with serialized data encoded using Manchester coding scheme. The deserializer on the hub handles the bit period uncertainty by counting and extracting the bit period of received data with a clock only ~2.2× faster than the serializer clock. The proposed counting-based Manchester decoder achieves a wide frequency coverage up to 204,000 ppm of frequency variation. The deserializer achieves a measured Manchester decoding bit error rate < 10 -6 , with a total estimated power consumption below 415 µW. The SerDes performance has been validated with in vivo pre-recorded data, demonstrating a compression ratio greater than 7, while preserving a high signal fidelity with an average RMSE < 6 µV RMS .

Abstract In reservoir computing, the memory decay rate of physical reservoir nodes governs how quickly past inputs fade, thereby determining their temporal dynamics. Optimizing this rate is therefore crucial for effective temporal signal processing. However, in most reported
physical reservoirs, it is fixed at the time of fabrication and cannot be altered on demand for different applications. Thus, tailoring a single node for its adaptability across tasks with diverse temporal characteristics remains challenging. In this work, we propose and
computationally analyse a CMOS-compatible, tunable-decay, hybrid reservoir node that integrates a subthreshold-operated FET with a programmable ReRAM device (a memristor) and a capacitor connected at its gate terminal. The reservoir output measured as the FET drain current simultaneously captures temporal memory and nonlinear transformation of the input, while the memory decay time constant (τ = R × C) can be modulated in real time by adjusting the ReRAM resistance. We demonstrate the effectiveness of the proposed node on two representative benchmark tasks with contrasting τ requirements, namely, the MNIST digit classification with 96% accuracy, and a chaotic Henon map prediction with a normalised RMS error of 0.0037, matching state-of-the-art hardware reservoirs. Our design achieves ultra-low energy consumption (≈ 15.20 pJ/operation), at least an order of magnitude lower than state-of-the-art implementations, while maintaining reliable operation and on-demand τ tunability. This combination of mature silicon technology and adaptive memristive functionality paves the way for energy-efficient, scalable, and reliable temporal learning systems

Abstract Replicating the operation of biological neurons using electronic hardware is of significant interest for engineering and biomedical applications. Spiking neural network (SNN) models are especially suited as they exhibit temporal dynamics and local synaptic plasticity, closely mimicking biological neural function. To enable biological interaction, real-time response, and the ability to explore and deploy multiple neural models becomes also necessary. In this work, the Hardware Emulator of Evolving Neural Spiking Systems (HEENS), an efficient, fully digital architecture intended for real-time execution of SNNs, is reported. Based on Single Instruction Multiple Data (SIMD) computation, an array of simple but programmable processing elements is controlled by a sequencer dispatching common instructions. Local distributed memory avoids data bottlenecks and enables parallel parameter updates and interconnect reconfiguration. The address-encoded spikes are decoded by local associative memories, that can be modified on the fly, thus supporting evolvable networks. A synchronous ring topology based on fast point-to-point serial links enables multi-node systems with minimal latency and excellent scalability. A control node controls and configures the ring nodes, drives the system execution, and monitors the processed data. The hardware is supported by a user-friendly custom set of tools that performs a simple and fast compilation of neural/synaptic algorithms and network topology on a host computer. The results of field-programmable gate array (FPGA) implementation are reported. Multimodel real-time execution of proof-of-concept networks demonstrates the proposed architecture potential.

Abstract The increasing demand for faster, energy-efficient, and higher bandwidth semiconductor devices has pushed conventional Si-based scaling to its fundamental limits, including mobility degradation, short-channel effects, and high power consumption. To overcome these challenges, three-dimensional integration has emerged as a promising strategy, but wafer-based approaches like through-Si-via face critical limitations in stacking density, mechanical stress, and fabrication complexity. Two-dimensional materials provide a compelling alternative due to their atomically thin structure, superior electrical and mechanical properties, and ability to sustain performance at the atomic scale. Moreover, their van der Waals integration enables heterogeneous, high-density, and efficient assembly of functional layers. This review summarizes recent advances in the preparation and van der Waals integration of 2D materials, including growth, transfer, and direct integration. Their applications in intelligent computing that range from logic to sensor devices and their potential as next-generation electronics are discussed.

Abstract The human visual system can effectively sense optical information through the retina and process it at the visual cortex. Compared with conventional machine vision, it demonstrates superiority in terms of energy efficiency, adaptability, and accuracy. The retina-inspired machine vision systems can process information near or within the sensors at the front end, thereby compressing the raw sensory data and optimising the input to back-end processor for high-level computing tasks. In recent years, amid surge of AI technology, research in retinomorphic devices has achieved breakthrough in both academic and industrial settings. Herein, we present a comprehensive review of this emerging field based on several materials classes, such as halide perovskites, two-dimensional materials, organic materials and metal oxides. We discuss the steps taken towards achieving not only static pattern recognition, but also dynamic motion tracking and we identify the key challenges that need to be addressed by the community to push this technology forward.

Abstract In this work, we demonstrate the potential of HfO₂-based memristors as artificial synapses capable of reproducing biologically plausible spike-timing-dependent plasticity (STDP). W/HfO₂/Ti/TiN devices were fabricated and characterized, exhibiting reliable bipolar resistive switching, stable endurance, and reproducible resistance states across multiple cells and devices. The excitatory postsynaptic current (EPSC) response under sequential voltage pulses revealed gradual potentiation, depression, and saturation dynamics, closely resembling long-term potentiation, long-term depression, and synaptic consolidation in biological systems. Furthermore, the memristors successfully emulated higher-order learning rules, including triplet-STDP and frequency-dependent plasticity, while maintaining robust performance under biologically realistic noise conditions, exhibiting less than ±2% variation under voltage perturbations and ±2.5% under spike-timing jitter across 25 trials. A compact physical model captured the interplay between vacancy-driven filament dynamics and time-dependent weight modulation, yielding STDP curves consistent with experimental observations in neuroscience. These findings highlight HfO₂ memristors as promising candidates for neuromorphic computing, providing not only a faithful hardware realization of synaptic learning but also compatibility with large-scale, CMOS-integrated architectures for next-generation cognitive processors.