- New
- Research Article
- 10.1088/2634-4386/ae65d2
- May 14, 2026
- Neuromorphic Computing and Engineering
- Bruno Golosio + 12 more
- New
- Research Article
- 10.1088/2634-4386/ae6728
- May 14, 2026
- Neuromorphic Computing and Engineering
- Zhou Biyan + 1 more
- New
- Research Article
- 10.1088/2634-4386/ae65d5
- May 13, 2026
- Neuromorphic Computing and Engineering
- Ankit Bende + 9 more
- New
- Research Article
- 10.1088/2634-4386/ae65d0
- May 12, 2026
- Neuromorphic Computing and Engineering
- Soufiyan Bahadi + 2 more
- New
- Research Article
- 10.1088/2634-4386/ae65d3
- May 12, 2026
- Neuromorphic Computing and Engineering
- Shiquan Yan + 6 more
- New
- Research Article
- 10.1088/2634-4386/ae65d4
- May 11, 2026
- Neuromorphic Computing and Engineering
- Bram F Haverkort + 3 more
- New
- Research Article
- 10.1088/2634-4386/ae5fc6
- May 4, 2026
- Neuromorphic Computing and Engineering
- Noriyuki Miyata
- New
- Research Article
- 10.1088/2634-4386/ae66b2
- Apr 29, 2026
- Neuromorphic Computing and Engineering
- Ckristian Duran + 3 more
Abstract The increasing complexity and energy demands of large-scale neural networks, such as Deep Neural Networks (DNNs) and Large Language Models (LLMs), challenge their practical deployment in edge applications due to high power consumption, area requirements, and privacy concerns. Spiking Neural Networks (SNNs), particularly in analog implementations, offer a promising low-power alternative but suffer from noise sensitivity and connectivity limitations. This work presents a novel CMOS-implemented field-programmable neural network architecture for hardware reservoir computing. We propose a Leaky Integrate-and-Fire (LIF) neuron circuit with integrated voltage-controlled oscillators (VCOs) and programmable weighted interconnections via an on-chip FPGA framework, enabling arbitrary reservoir configurations. The system demonstrates effective implementation of the FORCE algorithm learning, linear and non-linear memory capacity benchmarks, and NARMA10 tasks, both in simulation and actual chip measurements. The neuron design achieves compact area utilization (around 540 NAND2-equivalent units) and low energy consumption (21.7 pJ/pulse) without requiring ADCs for information readout, making it ideal for system-on-chip integration of reservoir computing. This architecture paves the way for scalable, energy-efficient neuromorphic systems capable of performing real-time learning and inference with high configurability and digital interfacing.
- New
- Research Article
- 10.1088/2634-4386/ae6369
- Apr 22, 2026
- Neuromorphic Computing and Engineering
- Hanna Honorine Hamrell + 2 more
Abstract Taking inspiration from the brain on how to create energy efficient and low latency
neuromorphic systems has the potential to create new opportunities with AI across many
domains. Firstly, it creates a possibility to mitigate problems with too large digital signal
processing costs in various technologies. Secondly, it also enables the use of AI and
machine learning algorithms where it is currently impossible due to energy constraints.
Recently, neuromorphic technology has been introduced to radio communication and radar
applications. In this work, we highlight advantages of applying energy efficient, low latency
and often lightweight neuromorphic computing for radar and radio signal processing. We
perform a comprehensive review of the main current works on neuromorphic technology
for radar applications, focusing on frequency-modulated continuous-wave and synthetic
aperture radar. Additionally, we cover radio frequency signal classification for both radar
and radio signals. Our ambition is to facilitate research on neuromorphic computing for
radar and radio systems, as well as help bringing researchers from these fields together.
- New
- Research Article
- 10.1088/2634-4386/ae629d
- Apr 21, 2026
- Neuromorphic Computing and Engineering
- Nico Reeb + 4 more
Abstract Radar sensors are a corner stone of autonomous driving, offering reliable perception under adverse weather and lighting conditions. However, the increasing resolution of modern automotive radar systems generates large data volumes that must be processed in real time, imposing significant computational and energy demands. This challenge is particularly acute in energy-constrained platforms such as electric vehicles and embedded devices, where power efficiency is critical. Neuromorphic computing offers a promising alternative by emulating the brain's event-driven and energy-efficient information processing. In this work, we extend existing resonate-and-fire neuron models, called spiking neural resonators (SpiNRs), into the Doppler domain to enable velocity estimation. We integrate SpiNR with a spiking Ordered Statistics Constant False Alarm Rate (OS-CFAR) algorithm to realize a full neuromorphic peak detection. Crucially, we introduce a novel activity-gated sparsity mechanism that dynamically deactivates inactive resonators, substantially reducing energy consumption while preserving estimation fidelity. All neuromorphic algorithms are implemented on Intel's Loihi 2 neuromorphic processor, which allows us to exploit event-driven computation and benchmark against conventional digital implementations under realistic hardware constraints. Evaluation against the conventional Fast Fourier Transform and classical OS-CFAR pipeline demonstrates that SpinR achieves competitive accuracy in range-velocity estimation. The proposed activity-gated sparsity mechanism yields additional energy savings and removes the need for a separate peak detection stage, further simplifying the processing chain. These findings highlight the potential of neuromorphic radar processing as a power-efficient alternative to conventional methods and underscore the importance of developing next-generation neuromorphic substrates optimized for embedded signal processing.