ABSTRACT As in many medical device systems development, the design of radiofrequency breast tumor detection systems undergoes a test phase based on the use of liquid phantoms. It is well known the difficulty in obtaining phantoms that precisely model each tissue for each frequency of interest while keeping such properties for a long time. Despite the many available studies using such phantoms, limited information is available on a systematic analysis of the effect that the use of an imprecise phantom may have on the characterization of radiofrequency systems. This work presents the design and fabrication of ultra‐wideband liquid breast and tumor phantoms. The main issue with this approach is that incorrect phantom properties, as well as an incorrect frequency response, lead to assessment errors. The current research focus is mainly focused on the model of the phantom, rather than its electromagnetic properties. Typically, the EM properties of breast phantoms are accurate only in a small frequency range, and these properties are frequency dependent. To address this issue, we validated a homogeneous breast phantom with good results in terms of dielectric permittivity (1.613% < error < 3.22%) and loss tangent (error < 33%) in the wide frequency range of [1–6] GHz. The proposed phantom retains its properties for a significant period of time, degrading only 6.78% in 2 h after fabrication while exposed to the environment. When it is stored in a container, only a small variation of ±1.7% was registered after 9 months.

ABSTRACTThis research paper introduces an innovative voltage‐mode instrumentation amplifier circuit employing a single voltage differencing current conveyor (VDCC) in conjunction with four grounded resistors. The designed circuit provides two output signals with opposing phases. This work includes comprehensive analyses encompassing both ideal and non‐ideal circuit behaviors. To validate the theoretical findings, we conducted SPICE simulations utilizing 0.18 μm CMOS process parameters. The proposed circuit exhibits a substantial differential‐mode gain of 32 dB and a notable bandwidth of 21.93 MHz. Furthermore, it demonstrates a remarkable common‐mode rejection ratio (CMRR) of 91.1 dB, with a CMRR bandwidth of 405.3 kHz. Operating within a ±0.9 V range, the circuit's power consumption remains notably low, measuring at a mere 0.6 mW. The circuit's robustness was rigorously tested through extensive simulations, and its performance under process–voltage–temperature variations was thoroughly assessed. To validate its practical viability, we conducted experimental tests using commercially available AD844 and LM13700 ICs.

ABSTRACT Compared to traditional technology computer‐aided design (TCAD) simulations, using neural networks to predict semiconductor device performance does not face convergence problems. This advantage is particularly significant when simulating devices made of materials like silicon carbide (SiC), which exhibit complex physical behaviors, making them difficult to converge in simulations. In addition, traditional TCAD software lacks the capability to deduce device structural parameters from device performance metrics. This article selects four critical structural parameters of 4H‐SiC trench gate MOS devices: trench depth ( D t ), gate oxide thickness ( T ox ), drift region doping concentration ( N d ), and P‐region channel P‐region length (L) as variables. Firstly, two types of neural network architectures were constructed and trained to serve as a classifier and a value predictor, respectively, among them, the breakdown mechanism classifier achieved an accuracy rate of 97% in the validation process. The average error of breakdown voltage prediction was 5.6%. In order to ensure the accuracy and stability of the prediction, we randomly selected 1000 sets of parameters within the value range for simulation to obtain a new dataset and improve the neural network structure. The improved neural network achieved average errors of 2.9% and 4.9% in the prediction of breakdown voltage and on‐resistance, respectively. Subsequently, we built an optimizer based on the improved neural network, achieving an automated design process for device structural parameters according to target breakdown voltage and on‐resistance. In the accuracy validation of the optimizer, the average error between target values and actual values of breakdown voltage and on‐resistance is 2.5% and 7.9%, respectively.

ABSTRACTThe field of portable electronics and smart devices has seen a significant shift toward multi‐valued logic (MVL), especially ternary logic, due to its potential to reduce circuit complexity and power consumption. This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular, we propose a procedure to design CNTFET‐based NOR/NAND gates and a Decoder, all in ternary logic, and the proposed method allows us to evaluate the propagation delay. Comparing the proposed design with the existing design, the delay times are reduced by approximately 80%. Moreover, the main novelty is that in this paper all simulations are performed in Verilog‐A, thus avoiding the problems presented in SPICE. The obtained results are encouraging and demonstrate that CNTFET‐based ternary logic gates can be a viable approach for the design of low‐power, high‐speed circuits.

ABSTRACT This paper presents compact, low‐power, electronically tunable dual‐output filters implemented using DTMOS (dynamic threshold MOSFET) in a 0.18 μm CMOS process. The designs utilize intrinsic transistor parasitic capacitances to realize filter responses, eliminating the need for external passive components. Electronic tunability in both low‐pass and band‐pass outputs is achieved through the dynamic threshold MOSFET technique, allowing operation at a lower supply voltage with fewer components. The low‐pass filter's cut‐off frequency can be tuned from 237.2 kHz to 141.34 MHz, while the band‐pass filter's center frequency ranges from 218.3 kHz to 132.13 MHz. Three filter configurations are proposed to optimize frequency performance. Simulation results using Cadence–Virtuoso show an average power consumption of 0.213 mW at 1.6 V with a 15 pF load capacitor. The proposed filter design is ideal for integration into modern portable and power‐sensitive electronic systems due to its wide tuning range, low voltage operation, low power consumption, and compact size.

ABSTRACTOn the basis of the canonical section‐wise piecewise linear (CSWPL) technique, this work presents the novel modified drain and gate current models for advanced spice model (ASM) that take temperature effects into account. Compared with the classic ASM current model, the proposed approach incorporates an error‐correction module based on the CSWPL technique, providing enhanced prediction accuracy. In addition, temperature dependence is explicitly modeled through a polynomial function, enabling reliable performance across a wide temperature range. To experimentally validate the new model, multi‐temperature current measurement data obtained from a 0.25 × 440 μm2 gallium‐nitride (GaN) high‐electron‐mobility transistor (HEMT) are used. The achieved results demonstrate that the modified model significantly improves current prediction accuracy compared to the classic current model.

ABSTRACTBlack‐box optimization problems arise in many real‐world applications, where the objective function is unknown or computationally expensive to evaluate. In electromagnetic engineering, optimization tasks often involve complex structures and materials, making direct analytical solutions infeasible. These problems are further complicated by high‐dimensional search spaces, the need for numerous simulations, and the absence of explicit derivative information. Gradient‐based optimization methods are often impractical due to the lack of gradients and high evaluation costs. Even derivative‐free optimization (DFO) techniques may struggle with efficiency in high dimensions. To address these challenges, we implement a surrogate‐based adaptive sampling DFO approach that refines a surrogate model while optimizing black‐box electromagnetic problems. We focus on deterministic black‐box functions with noise‐free evaluations. Our methodology is demonstrated in two case studies: optimizing the reflection coefficient in a partially filled waveguide and the transmission properties of a multilayered dielectric filter. We compare our method against Monte Carlo, Polynomial Chaos, Genetic Algorithms, and Particle Swarm Optimization. We confirm that our approach achieves a better solution while maintaining high accuracy in the surrogate model, with significantly fewer simulations. For the waveguide problem, our method achieved a best value of 0.1325 using only 168 simulations, compared to 0.1374 with 100 million Monte Carlo samples and 0.1469 with 9180 Polynomial Chaos evaluations. In the filter case, we obtained 1.7113 GHz using 240 simulations, outperforming the 1.7682 GHz result from 5370 Polynomial Chaos samples. These results demonstrate a simulation cost reduction of over 95%–98%, while achieving improved optimization performance.

ABSTRACT The work presents the design of a compact two and four‐element multiple input multiple output (MIMO) antenna, featuring a self‐isolation capability. The proposed MIMO antenna operates at 0.77–0.96 GHz Global System for Mobile Communication (GSM‐900) and 3.4–3.8 GHz (sub‐6 GHz 5G band) for | S 11 | < −10 dB. The front view of the designed antenna comprises a thin slot that is sandwiched between the patch and an additional radiating element. Further, an inverted T‐shape ground has been incorporated to attain the dual‐band functionality without increasing the size of the antenna. Four antenna elements are placed orthogonally to enhance isolation between the inter‐spaced radiators. It provides high isolation of the order of 32 and 24 dB for the GSM and 5G bands, without the use of a decoupling element. The two‐port and four‐port MIMO antenna occupies a space of 38 × 23 mm 2 and 50 × 45 mm 2 on FR4 substrate with permittivity of 4.40. Furthermore, diversity characteristics have been evaluated based on crucial parameters like envelope correlation coefficient (ECC), diversity gain (DG), and channel capacity loss (CCL) which are computed, and corresponding values for these parameters are as ECC 0.02, DG 10, and CCL below 0.5 bits/s/Hz for the two‐port antenna. However, in the case of the four‐port MIMO antenna, diversity results are as ECC 0.005, DG 10, and CCL is below 0.4 bits/s/Hz, which shows that the diversity performance of the four‐port MIMO is better than the two‐port MIMO antenna. Further, the validation of results and performance parameters of the fabricated antenna are experimentally tested and verified with the simulation results. The proposed work is well suited for Internet‐of‐Things (IoT) and Biomedical applications with SAR values at 0.80 GHz/3.60 GHz for two/four ports corresponding to 0.000153 and 0.712 W/Kg for single‐port and 0.000473 and 0.0483 W/Kg for the four‐port MIMO antenna.

ABSTRACTCapacitance multipliers are essential in applications requiring large capacitance but constrained by size, cost, or integration feasibility. Their ability to simulate high‐value capacitors using active components makes them crucial in modern ICs, power electronics, biomedical devices, wireless communication, and sensor interfaces. This paper presents a novel approach for designing resistorless grounded capacitance multiplier (GCM) circuits. The proposed design employs the voltage differencing inverting buffered amplifier (VDIBA) as the active block, leading to the introduction of 18 new GCM circuits. These circuits utilize two VDIBAs and a single capacitor, enabling both positive and negative capacitance multiplication factors (MFs). The MF of all the presented circuits can be electronically tuned using bias voltages and also have independent control. The design eliminates stringent matching constraints, enhancing practical feasibility. Furthermore, the impact of nonideal VDIBA parasitics on circuit performance is thoroughly analyzed and compared with ideal values. To validate the proposed approach, the circuits are applied in the design of a first‐order low‐pass filter (LPF). Their functionality is further confirmed through a CMOS‐based VDIBA implementation using 0.18 μm TSMC technology parameters in PSPICE simulations. Comprehensive analyses, including frequency and transient response, Monte Carlo analysis, process corner evaluation, and temperature variation, demonstrate the robustness of the circuits. The proposed GCM circuits operate over a wide frequency range from 1 mHz to 0.1 GHz, making them suitable for applications such as signal processing, impedance matching, and noise filtering. The capacitance can be enhanced up to 20 times its original value, while the circuit consumes approximately 1.5 mW of power. Experimental frequency response of an application example of a LPF using a VDIBA, implemented with commercially available ICs CA3080 and AD830, is also provided.

ABSTRACT In this work, two approximation techniques are presented for solving nonlinear Volterra integro‐differential equations with boundary conditions, arising in the modeling of inelastic cables subjected to external loads. The foundation of the required numerical computation is established through the operational matrices of interpolating basis functions and the Gegenbauer wavelet technique, which transform the original problem into a system of algebraic equations. To construct the interpolation basis functions, orthonormal Lagrangian basis functions are employed. Subsequently, the resulting algebraic system is solved using Newton–Cotes nodes to obtain the desired numerical solution. The use of operational matrices simplifies the problem and significantly reduces the computational complexity of solving integro‐differential equations. Moreover, error bounds are established, and a comprehensive convergence analysis of the proposed methods is carried out. Finally, numerical experiments supported by graphical illustrations clearly demonstrate the reliability and computational efficiency of the developed techniques.