As the most fundamental and widely-used technique in molecular diagnostics, polymerase chain reaction (PCR) plays a crucial role across various applications including epidemic surveillance and medical diagnosis. For the numerous epidemics such as COVID-19, the massive and frequent detection has challenged the PCR equipment in system miniaturization and hardware cost efficiency as well as rapid and precise detection. In conventional methods, fluorescence-PCR requires huge costly optical instruments, and the DNA-Probe-PCR can only detect a corresponding sample. In addition, both the fluorescence-PCR and DNA-Probe-PCR suffer from complex pre-label or modification procedure, further increasing the fabrication cost. In this work, we demonstrate the first probe-free electrical-digital-PCR (EdPCR) chip based on impedance detection: 1) A sensor-on-circuit structure is proposed to replace the bulky costly optical instrument with a single CMOS chip, enabling the PCR equipment to be portable and disposable. 2) A harmonic-voting method is proposed to reduce the testing pixel error rate (PER). The system is implemented in 55nm CMOS process, and in-vitro PCR experiment is conducted in various samples. The on-chip sensing array of the proposed PCR chip achieves a pixel density of 1111 pixels/mm2, which is the highest in the state of the arts. Additionally, the proposed harmonic-voting method reduces the measured PER of impedance judgment by 35%, achieving an average PER of 12.2%.

Multi-channel neural recording enables simultaneous monitoring of neuronal activities across multiple brain regions, while the in-vivo common-mode interference (CMI) significantly degrades the signal quality of implantable neural-recording chips. For a multi-channel neural-recording chip, the total common-mode rejection ratio (T-CMRR) of the analog front-end (AFE) is limited by the input imbalance between the signal electrode and the shared reference electrode, as well as the intrinsic CMRR (I-CMRR) of its circuits. The traditional common-mode replication (CM-REP) technique is only applicable to single-channel systems such as ECG monitoring devices. In addition, conventional pre-amplifier and frequency-controlled differential regulator (FCDR) techniques suffer from gain mismatch and high power consumption, respectively. To address these issues, this work presents a 32-channel neural-recording chip fabricated in a 65 nm CMOS process, which effectively suppresses the CMI in two operational modes: 1) In high-gain mode, the proposed CM-tracking-dynamic-power-rail (CM-TDPR) instrumentation amplifier (IA) achieves 50 GΩ CM input impedance, 117 dB I-CMRR, and 100 dB power supply rejection ratio (PSRR), resulting in a T-CMRR of 87 dB; 2) In low-gain mode, a CM-canceling-in-idle-phase (CM-CIP) technique is proposed to increase the I-CMRR to 102 dB and match the signal-reference input impedance, thereby achieving a 95 dB T-CMRR. In-vivo experiments were conducted on a Sprague-Dawley rat, successfully validating the CMRR performance of the proposed chip.

Capsule robot has emerged as a non-invasive and painless diagnostic tool for gastrointestinal examination. However, the growing demand for high-definition video and advanced functionalities significantly increases power consumption, while the capsule's compact size imposes stringent battery constraints. Wireless power transfer (WPT) offers a promising solution to overcome this energy bottleneck. This paper presents a wearable three-dimensional transmitting coil (3DTC) and a one dimensional receiving coil (1DRC) to enable omnidirectional and uninterrupted wireless charging for capsule robots. By acquiring attitude data from the capsule, the magnetic field of the wearable 3DTC is adaptively controlled to maximise receiving efficiency despite changes in the capsule's position and orientation. The capsule's built-in thermal and charging management circuits monitor the device's temperature, battery voltage, and stop charging when necessary to ensure safety. Beyond demonstrating a maximum received power of 1690 mW and a peak efficiency of 16.09%, this work further examines a range of practical challenges including, the effects upon the flexible coil bending in garment, charging robustness under various capsule motions, and thermal safety. These evaluations contribute to safer, more efficient, and more sustainable ingestible biomedical devices.

Batteryless implantable medical devices (IMDs) require tens of μW to mW-level power while operating under stringent size constraints, uncertain post-implant orientation, and high body-channel attenuation that forces high-ratio voltage multiplication and slow energy accumulation. This paper presents a Inductive-Capacitive dual mode wireless power transfer (WPT) system that improves charging latency and link robustness by combining three techniques: (i) a split rectifier (REC) architecture with temporal energy combining to mitigate stage-leakage and accelerate energy accumulation, (ii) an orthogonal coil-fed cuboid receiver that provides spatially neutral (orientation-independent) operation, and (iii) dual-mode inductive-capacitive powering by reusing the same conductors as both inductive coils and capacitive electrodes. A load-isolating switch (LIS) further suppresses leakage during startup, reducing the average load-leakage. Fabricated in 65-nm CMOS, the 0.19 mm2 prototype achieves ~3.4× faster charging compared to the TEG/solar based prior-art design. In addition, under identical input conditions of -12 dBm at 70 MHz, the proposed 4 × 60-stage split-rectifier architecture demonstrates approximately 4× reduction in charging time compared to a conventional 240-stage implementation. The WPT system achieves a minimum input power sensitivity of -26 dBm (2.5 μW) and operates with input amplitudes down to ~30 mV, enabling compact, faststarting, and spatially robust wireless powering for IMDs.

The therapeutic efficacy of closed-loop neuromodulation is critically undermined by stimulation artifacts that create a prolonged amplifier blind period', obscuring neural biomarkers. While state-of-the-art solutions mitigate this by adding complexity around the amplifier-such as active reset, blanking, or digital cancellation-they introduce trade-offs like data loss or computational overhead. In a distinct departure from these approaches, this paper solves the problem at its root by introducing a state-aware feedback element: a self-adaptive pseudo-resistor (A-PR). The A-PR architecture integrates two key innovations: an adaptive Floating Power Supply (FPS) that senses DC errors and autonomously collapses the feedback resistance for rapid recovery, and a process-insensitive Self-Biased Current Source (SBCS) that ensures robust, uniform performance against PVT variations. A complete neural recording front-end featuring the A-PR was fabricated in a 40-nm CMOS process. Measurement results validate the core claims, demonstrating a sub-3-ms recovery time from a 1-V artifact, an input-referred noise of 5.23 µVrms, and a tunable high-pass corner, all while consuming only 2.3 µW and occupying 0.015 mm2. By eliminating the trade-off between fast recovery and high fidelity, the A-PR provides a scalable, low-power solution for next-generation, high-resolution closed-loop neural interfaces.

We present a 43 µm ${\boldsymbol{\times}}$ 269 µm tetherless neural recording microsystem in which the CMOS bulk is forward-biased to utilize silicon junctions as a photovoltaic source. Our microsystem, forward-bulk microscale optoelectronic tetherless electrode (FB-MOTE), can operate with as low as 0.2 µA at 0.317 V and can withstand light intensity up to 1200 µW/mm2, and is power-adaptive: the higher available power increases the system bandwidth while maintaining the input-referred integrated noise. To balance adaptability and stability, we have designed our amplifier to take up most of the additional power, hence acting like a regulator, while the other circuit blocks are PTAT-biased to remain relatively stable across available power levels. The amplified neural signals are pulse position modulated (PPM) and optically transmitted through an AlGaAs microscale light emitting diode (µLED) for its information-per-photon efficiency, where the µLED driver is designed to maximize the emission-to-area ratio. Finally, we discuss various light-induced effects observed in measurements and introduce a simulation methodology to account for such effects and its limitations. Our forward-bulk CMOS microsystem provides an approach that can effectively harness and account for the available light in optoelectronic systems design.