All Research Papers Published In IEEE Transactions on Very Large Scale Integration (VLSI) Systems | R Discovery

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Front Matter
10.1109/tvlsi.2026.3653071

Table of Contents

Feb 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

New
Research Article
10.1109/tvlsi.2025.3624325

ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication

Feb 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Atri Chatterjee + 2 more

Research Article
10.1109/tvlsi.2026.3657330

A 0.67–5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jared Mercier + 4 more

Research Article
10.1109/tvlsi.2026.3656525

HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC nand Flash Memory

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yongchao Wang + 4 more

Research Article
10.1109/tvlsi.2026.3651307

Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linjun Jiang + 3 more

Research Article
10.1109/tvlsi.2026.3658524

AccLLM: Accelerating Long-Context LLM Inference via Algorithm-Hardware Co-Design

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yanbiao Liang + 3 more

Research Article
10.1109/tvlsi.2025.3595897

Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thai-Ha Tran + 5 more

Research Article
10.1109/tvlsi.2026.3657208

A CIM Macro Embedded With Sign Operations for Parallel Signed Multibit Multiplication-and-Accumulation Using Hybrid Cell Array

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jin Zhang + 8 more

Research Article
10.1109/tvlsi.2025.3650162

A T8T-SRAM Computing-in-Memory Macro for Ternary Deep Neural Networks and Boolean Logic Computations

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chenghu Dai + 9 more

Research Article
10.1109/tvlsi.2025.3630648

A 28 nm 1.3 TFLOPS/mm <sup>2</sup> Floating-Point SRAM-Based CIM Macro With Asynchronous Normalization and Parallel Sorting Alignment for AI-Edge Chip

Jan 1, 2026
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Zhiting Lin + 9 more

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