This brief presents an on-chip digital intensive frequency-locked loop (DFLL)-based wakeup timer with a time-domain temperature compensation featuring a embedded temperature sensor. The proposed compensation exploits the deterministic temperature characteristics of two complementary resistors to stabilize the timer's operating frequency across the temperature by modulating the activation time window of the two resistors. As a result, it achieves a fine trimming step (± 1 ppm), allowing a small frequency error after trimming (<± 20 ppm). By reusing the DFLL structure, instead of employing a dedicated sensor, the temperature sensing operates in the background with negligible power (2 %) and hardware overhead (< 1 %). The chip is fabricated in 40 nm CMOS, resulting in 0.9 pJ/cycle energy efficiency while achieving 8 ppm/ºC from -40ºC to 80ºC.

Synchronous activities among neurons in the brain generate emergent network oscillations such as the hippocampal Sharp-wave ripples (SPWRs) that facilitate information processing during memory formation. However, how neurons and circuits are functionally organized to generate oscillations remains unresolved. Biophysical models of neuronal networks can shed light on how thousands of neurons interact in intricate circuits to generate such emergent SPWR network events. Here we developed a large-scale biophysically realistic neural network model of CA1 hippocampus with functionally organized circuit modules containing distinct types of neurons. Model simulations reproduced synaptic, cellular and network aspects of physiological SPWRs. The model provided insights into the role of neuronal types and their microcircuit motifs in generating SPWRs in the CA1 region. The model also suggests experimentally testable predictions including the role of specific neuron types in the genesis of hippocampal SPWRs.

This brief presents a frequency-modulation-based analog-to-digital converter (FM ADC) that takes advantage of the coding gain resulting from bandwidth expansion in the analog domain of FM systems to achieve high dynamic range and incorporates a highly digital demodulation approach for power efficiency. The novel architecture employs a sinusoidal output voltage-controlled oscillator (VCO), a relatively low-resolution successive approximation register ADC to sample signals in the FM domain, and then a digital signal processing FM demodulator to recover high-resolution samples of the VCO's original analog input. The proposed ADC is implemented in 0.5-mm2 of 65-nm CMOS; it achieves 104-dB DR, 99-dB SNR, and 71-dB SNDR in a 44-kHz bandwidth while dissipating 678 μW of power. The architecture of the FM ADC leverages analog domain processing for system performance and digital domain processing for lower power. This novel approach presents a viable alternative to delta-sigma converters for high dynamic range conversion in advanced process nodes.

A supply-doubled pulse-shaping high voltage (HV) pulser is presented for medical ultrasound imaging applications, particularly those that use capacitive micromachined ultrasonic transducers (CMUT). The pulser employs a bootstrap circuit combined with dynamically-biased stacked transistors, which allow HV operation above process limit without lowering device reliability. The new pulser overcomes supply voltage limitation of conventional unipolar pulsers by generating output signals that are almost twice the supply level. It also can generate three-level pulses to further optimize the transmit pressure signals. A proof-of-concept prototype has been implemented in 0.18-μm HV CMOS/DMOS technology with 60 V devices. Measurement results show that the HV pulser can safely generate controllable three-level pulses with up to 85 Vpp from 45 V supply. Acoustic measurements are conducted connecting the pulser to a CMUT with 2 pF capacitance and 8.3 MHz center frequency. The pulse shape has been adjusted for the CMUT under test to generate maximum pressure output and the results are in good agreement with a large signal CMUT model.

This brief presents a frequency-domain analysis of the latch comparator offset due to load capacitor mismatch. Although the analysis is applied to the static latch comparator, the developed method can be extended to the dynamic latch comparator.

The Tongue Drive System (TDS) is a new unobtrusive, wireless, and wearable assistive device that allows for real-time tracking of the voluntary tongue motion in the oral space for communication, control, and navigation applications. The latest TDS prototype appears as a wireless headphone and has been tested in human subject trials. However, the robustness of the external TDS (eTDS) in real-life outdoor conditions may not meet safety regulations because of the limited mechanical stability of the headset. The intraoral TDS (iTDS), which is in the shape of a dental retainer, firmly clasps to the upper teeth and resists sensor misplacement. However, the iTDS has more restrictions on its dimensions, limiting the battery size and consequently requiring a considerable reduction in its power consumption to operate over an extended period of two days on a single charge. In this brief, we propose an ultralow-power local processor for the TDS that performs all signal processing on the transmitter side, following the sensors. Assuming the TDS user on average issuing one command/s, implementing the computational engine reduces the data volume that needs to be wirelessly transmitted to a PC or smartphone by a factor of 1500×, from 12 kb/s to ~8 b/s. The proposed design is implemented on an ultralow-power IGLOO nano field-programmable gate array (FPGA) and is tested on AGLN250 prototype board. According to our post-place-and-route results, implementing the engine on the FPGA significantly drops the required data transmission, while an application-specific integrated circuit (ASIC) implementation in a 65-nm CMOS results in a 15× power saving compared to the FPGA solution and occupies a 0.02-mm2 footprint. As a result, the power consumption and size of the iTDS will be significantly reduced through the use of a much smaller rechargeable battery. Moreover, the system can operate longer following every recharge, improving the iTDS usability.