As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multiple efforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of over 680 000 fully connected and convolutional neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, and the average performance across a subset of the dataset. Additionally, we introduce GNN- and transformer-based surrogate models that predict latency and resources for ML accelerators. We present the architecture and performance of the models and find that the models generally predict latency and resources for the 75% percentile within several percent of the synthesized resources on the synthetic test dataset.

Content Addressable Memories (CAMs) offer high-speed, deterministic lookups but face significant scalability challenges with large input keys ( \(>\) 100 bits), leading to excessive power, silicon area, and memory costs. This paper introduces Probabilistic Content Addressable Memory (P-CAM), a novel architecture designed to overcome these limitations by trading strict determinism for memory efficiency and scalability. P-CAM compresses high-dimensional inputs into fixed-size fingerprints using hashing, making memory requirements independent of key length. P-CAM preserves the constant-time lookup advantage of CAMs, while supporting applications with large keys, such as networking, bioinformatics, and machine learning, where conventional CAMs are impractical. FPGA implementation on Xilinx UltraScale+ devices shows that P-CAM maintains constant query latency and delivers 15 \(\times\) improvement in resource efficiency when handling 384-bit keys, compared to state-of-the-art deterministic CAMs designed for narrower inputs. Although P-CAM's probabilistic nature introduces a small, controllable false-positive rate, it can be configured for fully deterministic operation under specific constraints. To the best of our knowledge, P-CAM is the first CAM architecture to employ a fingerprint-based probabilistic data structure as the primary storage mechanism for associative lookup, distinguishing it from prior probabilistic approaches that are limited to set membership checks, offering a robust and scalable alternative for modern data-intensive systems.

Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open sourced and integrated into the hls4ml library, a free and open source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.

The rapid advancement of cloud computing has facilitated the widespread integration of field-programmable gate arrays (FPGAs) into cloud servers to accelerate computing processes. To reduce costs, cloud service providers aim to promote multi-tenant sharing of a single FPGA. In multi-tenant environments, tenants share the power distribution network (PDN), which introduces potential security vulnerabilities. Malicious tenants can conduct remote power analysis attacks by deploying on-chip voltage sensors to detect voltage fluctuations in the PDN. Previous research has focused on enhancing the flexibility and stealthiness of sensors, while insufficient attention has been paid to optimizing sensor parameters for accurate power measurement. This work introduces a phase tuning method for voltage sensors in remote power analysis attacks on AES. The experimental results demonstrate that adjusting the sampling phase enhances the performance of correlation power analysis (CPA) attacks. On average, this method reduces the number of power traces required for CPA attacks by 43.1% and improves the average ranking of correct subkeys by 1.968×. The work reveals novel security threats in multi-tenant FPGAs and contributes to advancing cloud FPGA security research.

Control and Status Registers (CSRs) are fundamental to the RISC-V architecture, providing a versatile interface for managing processor state, system configuration, and functionality like exception handling, debugging, and performance monitoring. However, their implementation in FPGA-based systems poses challenges due to the inherent constraints of FPGA resources. The need for atomic parallel access to all CSRs, coupled with limitations of conventional LUT-based multiplexing, increases logic depth and resource usage, degrading Fmax in large-scale implementations. This work explores these obstacles and introduces optimized mechanisms to improve CSR handling efficiency. A minimal microarchitectural environment was built to isolate and evaluate multiple access strategies, retaining only components essential to CSR interaction. Leveraging a heterogeneous design tailored to FPGA capabilities—featuring BRAM for decoding, DSPs for multiplexing, and LUTs, CARRYs and flip-flops to facilitate routing—the proposed CSR subsystem achieves performance enhancements ranging from 50% to over 300%, contingent upon configuration. The top-performing implementation reaches 250 MHz on Artix-7 FPGAs while simultaneously reducing area and dynamic power. These results challenge prevailing reliance on abstract electronic design, highlighting that hardware-aware low-level methodologies can yield superior quality-of-results (QoR) over pure behavioral descriptions. More broadly, the findings inform datapath optimization involving decoding and multiplexing in performance-critical and resource-constrained digital architectures.

High-speed non-volatile memory express (NVMe) solid-state drives (SSDs) are shared by multiple tenants in cloud scenarios to improve resource utilization. Tenant-level I/O management is necessary to achieve reliable QoS control during sharing. Unfortunately, our investigation finds that CPUs inevitably participate in I/O management for existing solutions because SSDs are not tenant-sensitive and have limited internal computing resources. It introduces additional CPU costs and latency overhead when serving future faster SSDs. We propose that the Field Programmable Logic Gate Array (FPGA) is a promising alternative for freeing tenant-level I/O management from CPUs. However, implementing tenant-level I/O management using the FPGA requires addressing the following challenges: (1) System compatibility and tenant identification. (2) Efficient FPGA workflows that will not become a bottleneck. (3) Fast I/O management workflow that introduces the lowest additional CPU costs and latency. This paper presents Zero2M, a novel CPU-free system designed to optimize the additional CPU costs and latency overhead in tenant-level I/O management for future faster NVMe SSDs. Zero2M proposes a dedicated FPGA-based NVMe controller to preserve system compatibility and identify tenants using the namespace mechanism in NVMe. It allows I/O management without modifying host software, which existing solutions cannot achieve. The parallelized and pipelined workflows are proposed in the controller to accelerate I/O command processing and prevent the controller from becoming a bottleneck for the I/O management workflow. The read/write speed of the Zero2M controller is 4.65 \(\times\) /4.92 \(\times\) faster than the state-of-the-art hardware-accelerated controller. The I/O management workflow is formulated as a novel parallelized and pipelined accelerator and integrated into the workflow of Zero2M's controller. It optimizes additional CPU costs and latency overhead for tenant-level I/O management. Experiments present that Zero2M reduces an average of 3.01 \(\times\) CPU usage while maintaining the lowest latency overhead (7.62 \(\times\) lower on average) compared to the state-of-the-art solution. It also removes the CPU dependency for tenant-level I/O management for the first time.

General-purpose compilers abstract away parallelism, locality, and synchronization, limiting their effectiveness on modern spatial architectures. As modern computing architectures increasingly rely on fine-grained control over data movement, execution order, and compute placement for performance, compiler infrastructure must provide explicit mechanisms for orchestrating compute and data to fully exploit such architectures. We introduce MLIR-AIR, a novel, open-source compiler stack built on MLIR that bridges the semantic gap between high-level workloads and fine-grained spatial architectures such as AMD’s NPUs. MLIR-AIR defines the AIR dialect, which provides structured representations for asynchronous and hierarchical operations across compute and memory resources. AIR primitives allow the compiler to orchestrate spatial scheduling, distribute computation across hardware regions, and overlap communication with computation without relying on ad hoc runtime coordination or manual scheduling. We demonstrate MLIR-AIR’s capabilities through two case studies: matrix multiplication and the multi-head attention block from the LLaMA 2 model. For matrix multiplication, MLIR-AIR achieves up to 78.7% compute efficiency and generates implementations with performance almost identical to state-of-the-art, hand-optimized matrix multiplication written using the lower-level, close-to-metal MLIR-AIE framework. For multi-head attention, we demonstrate that the AIR interface supports fused implementations using approximately 150 lines of code, enabling tractable expression of complex workloads with efficient mapping to spatial hardware. MLIR-AIR transforms high-level structured control flow into spatial programs that efficiently utilize the compute fabric and memory hierarchy of an NPU, leveraging asynchronous execution, tiling, and communication overlap through compiler-managed scheduling.

To enhance the storage efficiency of large datasets, big data analytics commonly rely on columnar file formats, such as Apache ORC (Optimized Row Columnar), to encode and compress data. These formats significantly reduce storage requirements and improve query performance by supporting efficient data organization and compression techniques. However, the use of such file formats introduces a new challenge: while high-bandwidth SSDs mitigate the I/O bottleneck, the computational burden of decompressing and decoding these formats shifts the bottleneck to the CPU. This computational overhead becomes a critical challenge in achieving high-throughput data processing. This work introduces FORCv2, a high-performance streaming-based FPGA accelerator overlay designed to overcome these limitations. First, FORCv2 integrates multi-PE Zlib decompression which leverages Xilinx’s high-performance single-PE (processing element) implementation and enhances performance with multi-way parallelism. Second, it features fully pipelined data decoding, optimized to achieve throughput close to the memory bandwidth of a single HBM channel, ensuring high-efficiency processing of ORC files. Third, FORCv2 incorporates flexible and efficient filtering capabilities, supporting both pre-stored indices and user-defined filter conditions for versatile data processing. Finally, it provides seamless dataflow integration with the Apache ORC library, enabling efficient end-to-end processing of ORC file formats. The proposed design leverages the inherent parallelism and high-bandwidth memory (HBM) capabilities of AMD/Xilinx Alveo U280 FPGAs to deliver exceptional performance. By employing a fully pipelined architecture and resource-efficient design, FORCv2 achieves up to 2.8 GB/s of overall throughput (input throughput). Considering all operators combined, on average, it provides end-to-end speedups of approximately 52x for the synthetic dataset and 39x for the TPC-H dataset, versus the ORC C++ library running on a dual-socket system with 48 CPU threads. Experimental evaluations demonstrate the effectiveness of FORCv2 across diverse workloads, showcasing its potential to handle real-world big data processing scenarios efficiently. The FORCv2 implementation will be open-sourced at https://github.com/SFU-HiAccel/FORC.

Field Programmable Gate Arrays (FPGA) have seen an increase in popularity in High-Performance Computing (HPC) environments due to their high flexibility and energy efficiency. However, the adoption of these devices for HPC application acceleration is relatively new, and their application is still focused on niche applications mainly due to the programmability issues FPGAs have traditionally faced. In this work, we present an open-source toolchain with support for different FPGA devices and memory topologies, and for implicit and explicit message-passing multi-node and multi-FPGA programming models, which, to the best of our knowledge, is the first of its kind available. The presented toolchain tries to address the increased complexity of programming newer multi-die devices using High-Bandwidth Memory (HBM) by proposing and evaluating HBM design strategies as well as inter-FPGA communication. In addition to presenting the framework characteristics, we evaluate its performance results over a cluster of FPGAs for a set of HPC application benchmarks delivering performance improvements over previous implementations in both single and multi-node versions. The presented framework is an ongoing effort to solve the lack of mature tools and ecosystems that allow programming large clusters of FPGAs, and consequently make scaling applications across multiple FPGA devices a simpler task.

Deep Packet Inspection (DPI) faces significant bottlenecks in regular expression (regex) matching due to escalating rule complexity and traffic volume. Existing FPGA-based solutions inefficiently process all packets through every automaton, incurring substantial resource overhead. This article proposes OD-REM, an on-demand regex matching architecture for FPGAs that dramatically improves efficiency. In addition to this novel architecture, OD-REM also introduces three innovations: (1) A Counter-Enabled Fast Reconfigurable Automaton (cFRA) compresses regex states by 97.5% via counting semantics, eliminating state explosion for bounded repetitions; (2) A Ring Queue (RQ) scheduler dynamically dispatches packets only to automata relevant to their candidate rules (identified via pre-filtering); (3) A modular pipeline for per-packet, on-chip run-time reconfiguration. Implemented on a Xilinx VU9P FPGA with 32 parallel cFRAs, OD-REM achieves 41.18 Gbps throughput—roughly 3× to 40× higher than the similar works while still performing a full reconfiguration on every packet. It reduces packet latency by 3.73 µs versus sliding-window scheduling. Integrated with Pigasus, OD-REM offloads complex rules, accelerating Hyperscan software matching by up to 37×. This work demonstrates FPGA-centric regex matching as a scalable, high-throughput solution for modern DPI systems.