This paper deals with the properties of the second Hall network in details, by a comprehensive analysis and simulation. Both normal form of the network and its reoriented version are considered – the first one being a band-stop and the latter a band-pass filter. Interestingly, the band-stop version gives an over unity gain.

A new full-custom design of Unary-to-Ternary-Encoder (UTE) using standard Enhancement-Type-Metal–Oxide-Semiconductor-Field-Effect-Transistor reporting low-PDP (Power-Delay-Product) and low-area is presented. The inherent pass characteristic of the E-MOS-transistor is exploited here to develop the proposed Ternary-Encoder. Theoretical aspects along with the operation of proposed 9:2 and 27:3 UTE are discussed. The complete UTE is designed and optimized on 32 nm standard CMOS technology at 0.9 V supply-rail and 27°C. Ternary digits “0”, “1” and “2” are represented with 0 V, 0.45 V and 0.9 V respectively. The proposed design is validated through extensive T-Spice front-end transient simulations with all possible test patterns. The layout of the proposed design is completed on 32 nm Single-Poly-Double-Metal (SPDM) CMOS--Technology. After DRC and LVS post-layout simulation with extracted parasitic and 1 fF load, is carried out. The valuated performance of the 9:2 UTE is next compared with a recent candidate design to this end, from open literature to benchmark. The Power-Delay-Product (PDP) of proposed UTE is measured by applying ±10% supply variation from nominal on slow, typical and fast MOSFET at −40°C, 27°C and 85°C. Finally, the speed-power characteristic of the proposed 9:2 UTE is explored under different load conditions from 1 to 10 fF.

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.

On the basis of remote sensing images, land cover change detection (LCCD) has gained popularity. Even though several techniques have been promoted lately, their effectiveness and usability still need to be improved. To assist urban sustainable development, evaluate natural disasters, and analyze the environment, very high-resolution (VHR) remote sensing images can be used to detect land cover change. Planning professionals can evaluate changes in land cover using remote sensing and geographic information systems, which have a reputation for excellence. A fully convolutional two-stream architecture is used in this paper to first extract highly representative deep features from bi-temporal images. After that, a Lenet5 is given the deep features to segment the land changes and detect changes. With the help of Faster-RCNN the land change classes are classified. We implement the proposed model in Python and conduct experiments on the land cover dataset. The outcomes of the experiments demonstrate that the proposed method outperformed previous deep learning algorithms, achieving the best accuracy, precision, recall, and F1-score.

An H-shaped slotted leaky-wave antenna (LWA) is proposed based on balanced composite right/left-handed (CRLH) transmission lines (TLs) to improve the backward scanning bandwidth and achieve constant gain. The proposed antenna consists of a substrate-integrated waveguide (SIW) unit cell array configured by an H-shaped slot cut in the top layer of the SIW and a patch embedded beneath the H-shaped slot. The proposed design improves the backward scanning bandwidth compared to planar SIW LWAs. The measured beam radiation is in the range from −79° to 80° over the frequency range of 7.6–12.5 GHz. Moreover, a constant gain of greater than 10 dB is achieved over the entire X-band frequency range.

We, the Editor, Institution and Publisher of the journal IETE Journal of Research, have retracted the following article, which is part of the Special Issue titled “Federated Learning for Blockchain Systems and Industrial Internet of Things”: Mohammad Dehghani, Pavel Trojovský, Štěpán Hubálovský, Theyab R. Alsenani & Jaswinder Singh (2022) Three-Periods Optimization Algorithm: A New Method for Solving Various Optimization Problems, IETE Journal of Research, DOI: 10.1080/03772063.2022.2052982 Following publication, concerns were raised about the peer review and decision-making processes for this special issue. After an investigation by the Taylor & Francis Publishing Ethics & Integrity team, in full cooperation with the Editor-in-Chief and the Institution, it was confirmed that the articles included in this special issue were not reviewed appropriately, in line with the Journal's peer review standards and policy. As the stringency of the peer review process is core to the integrity of the publication process, the Editor and Publisher have decided to retract all of the articles within the above-named Special Issue. The journal has not confirmed if the authors were aware of this compromised peer review process. The journal is committed to correcting the scientific record and will fully cooperate with any institutional investigations into this matter. The authors have been informed of this decision. We have been informed in our decision-making by our editorial policies and the COPE guidelines.  The retracted articles will remain online to maintain the scholarly record, but they will be digitally watermarked on each page as ‘Retracted’.

In this manuscript, a Meander Delay System design using Caps-Triple GAN optimized with the Remora Optimization Algorithm (ROA) is proposed for the Internet of Things (IoT) application. For designing the Meander Microstrip Delay Line (MMDL) Antenna, the Capsule Triple generative adversarial network (Caps-Triple GAN) is used. The Caps-Triple GAN error and delay parameters are optimized using the ROA. Hence, the designed MMDL Antenna is available in the IoT application. The proposed method is executed in the commercial Sonnet software package. The performance of the proposed method is examined under performance metrics, such as delay time with resistance characteristic, one-step delay time resistance characteristic, delay time, one-step delay time, error, and speed. The prediction results of the proposed MMDL-CAPS-Triple GAN-ROA method predict lower delay times of 14.77%, 15.89%, and 11.50%, higher speed of 32.57%, 16.25%, and 8.44% compared with the existing methods, such as Prediction of the meander delay system parameters for internet-of-things devices utilizing a Pareto-optimal artificial neural network and multiple linear regression (MDS-ANN-MLR), Predicting the frequency characteristics of hybrid meander systems utilizing the feed-forward back propagation network (MDS-FFBPN), Frequency Characteristic Analysis of Meander Structures with Different Connecting Electrodes (MDS-MoM), respectively.