Gate-oxide degradation is a concern in SiC MOSFETs especially in safety critical applications such as aerospace and electric vehicles (EV). To address this concern, this paper presents an accurate gate-oxide degradation monitoring solution based on the SiC devices’ transfer characteristics. Specifically, a plug-in circuit for gate driver is proposed to extract the transconductance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ) and threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_th</i> ) values from transfer characteristic. By using the threshold voltage as gate-oxide aging reference and transconductance as the junction temperature reference, the two precursors are combined to obtain a temperature and package degradation independent estimate of the gate-oxide health. High-temperature gate bias (HTGB) and DC power cycling tests are used to confirm <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ’s sensitivity to gate-oxide degradation and insensitivity to package degradation in kelvin-sourced discrete SiC MOSFETs. A simple circuit is proposed for on-board <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> measurement using the voltage drop on the common source inductance of the MOSFET. The measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> is converted into digital pulse width, which can be easily measured using a microcontroller. A comprehensive comparison is presented to demonstrate the merits of the proposed method. Lastly, the accuracy and sensitivity of temperature and aging measurements using the proposed method is validated experimentally.

The performance of semiconductor devices during board-level reliability (BLR) thermal cycling tests continues to be a concern in different applications. The primary focus of those BLR tests is to evaluate the fatigue life of external solder joints between the package and printed circuit board (PCB). For flip-chip ball grid array (FCBGA) package technology, internal solder bumps can also crack and result in open electrical failure. This type of BLR failure has yet to be widely reported in the literature. This article presents failures due to internal solder bump cracks during the BLR test. Failure analysis (FA) clearly shows the cracking location strongly depends on bump density. Finite Element Analysis (FEA) based simulation is performed to understand the failure mechanism. Unlike the standard BLR modeling approach, which focuses on predicting external solder joint fatigue life with correlated data, simulation here has to capture the entire internal bump pattern in the global BLR model. The need to capture the entirety of the bump scheme poses a significant challenge to managing the global model size with a reasonable meshing count and running time. Therefore, a customized post-process approach is developed to analyze bump density impact and enable design optimization.

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a $2^{31}-1$ pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of $10^{-12}$ .

&lt;p&gt;This article studies the performance of the proposed stereo matchingalgorithm on complex regions. These regions are areas with very limitedinformation for the matching process which are low texture, and depthdiscontinuity regions. In this study, each algorithm uses different matchingcost computation (MCC) techniques, but for cost aggregation (CA), disparityoptimization (DO) and disparity refinement (DR), the technique remains thesame. The MCC areabsolute difference(AD), the combination ofabsolutedifference and gradient matching(AD+GM) andcensus transform(CT).Then, for CA, DO and DR, they areminimum spanning tree(MST),winnertake all(WTA) andbilateral filter(BF), respectively. The results are presentedand discussed in this article. Hence, thru this study the robust method can beestimated at the MCC stage.&lt;/p&gt;

Abstract Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.

Piezoelectric power converters, where acoustic resonators replace the inductors as energy storage elements, promise much higher power density and higher efficiency compared to conventional circuits. Recently, lithium niobate (LiNbO3) piezoelectric resonators have been integrated within power converter circuits, showing good conversion efficiency, thanks to their high quality factor (Q) and electromechanical coupling (kt2). However, the converter output power range is limited by large spurious modes near resonance. This work reports a near-spurious-free LiNbO3 thickness shear (TS) resonator, demonstrating high Q of 3500 and kt2 of 45% at 5.94 MHz, with a fractional suppressed region of 35%. First, we identify the best LiNbO3 crystal orientation for efficient TS resonators. Then, we propose a novel acoustic design without busbars for spurious suppression, which is extensively simulated, fabricated, and characterized. Further analysis is done to identify existing spurious modes in our proposed design, specifically the effect of dicing on our TS resonator design. Upon optimization, LiNbO3 TS resonators could potentially empower a new design space for low-loss and compact power converters.