Yield improvement in wafer planarization: Modeling and simulation

Abstract

Chemical mechanical polishing (CMP) is a planarization process that produces high-quality surfaces both locally and globally. CMP is one of the key process steps during the fabrication of very large scale integrated (VLSI) chips in integrated circuit manufacturing. CMP consists of a chemical process and a mechanical process being performed together to reduce height variation across a wafer. High and reliable wafer yield, which is dependent on uniformity of the material removal rate across the entire wafer, is of critical importance in the CMP process. In this paper, the variations in the material removal rate across the wafer are analytically modeled assuming a rigid wafer and a flexible polishing pad. The wafer pad contact is modeled as the indentation of a rigid indenter on an elastic half-space. The model predictions are first verified against experimental observations. Simulation results for wafer yield under open-loop processing conditions are presented. Wafer curvature is identified as a key design variable influencing the spatial distribution of the material removal rate. The proposed model can be applied to control wafer-scale material removal rate variations in a CMP process.