WITHDRAWN: Performance analysis and design of finfet 32 nm based low power, low delay 4-bit alu, carry save adder and multiplier for high speed processors

Abstract

Abstract The limitations of CMOS technology are short channel effects, battery powered problem, power dissipation, delay. All digital circuits like logical and arithmetic operations are performed and designed using CMOS. The power dissipation/consumption in such circuits are more so the fast growing technology requires the lower power dissipation/consumption, low leakage currents and lessor short channel effects. Therefore, to address these issues, the proposed research work has introduced FinFET 32 nm technology for the designing of logical operation, arithmetic, multiplexer, 4-bit ALU, Carry Save Adder (CSA) and multiplier using Cadence Virtuosos software tool. Another challenge in CMOS technology is, size of the transistor which is used to measure area, therefore the proposed research work, optimize the delay, power, W/L ratio and also no of transistors for designing of both gates and arithmetic operations. The work has been carried out from schematic level to layout design to Graphic Data System (GDS II) generation. To validate the FinFET based ALU and multiplier, its detailed analysis of the constraints related to FinFET transistor level and benefits, in which each transistor is modified for the delay at different timings arcs and power consumption, are done. The individual gate and arithmetic operations are tested and calculated in which the delay and power consumption are compared with existing work and it is found that the reduction in the power level for AND, XOR, OR, NAND, NOT gates, full adder, CSA, 2bit multiplier and ALU are 36.09 nW, 61.13nW, 64.97nW, 37.45nW, 33.31nW, 38.22nW, 2.39 μW, 39.89nW and 314.4 μW respectively.