Wideband Inductorless True Time Delay Cell Based on CMOS Inverter for Timed Array Receivers

Abstract

In this paper, an inverter-based true time delay (TTD) cell for timed array receivers is proposed. The proposed TTD cell is designed in TSMC 0.18 µm CMOS technology for multi-GHz operations. The delay cell is made from an all-pass filter by Pade approximation. The first-order all-pass filter is built by combining a constant gain stage and a low pass stage based on the approximation. The constant gain stage consists of two NMOS transistors. The low pass stage is created with an inverter cell, cascaded with a PMOS transistor. Active true time delay cells are used in delay lines (commonly in cascaded topology) to develop a timed array system. Because of that, size of the TTD cell is critical and is an important design factor. So in this paper, an inductorless inverter-based wideband TTD cell is proposed. The wideband input impedance matching is achieved without bulky inductors using the resistive feedback technique in the inverter cell. More than wideband input impedance matching, flat gain, and flat delay response for the TTD cell are obtained with this technique. With the inverter-based input and complementary output structure, the TTD cell is a self-biased circuit. So, additional bias circuit is not needed. The proposed TTD cell consumes 8.7 mW from a 1.8 V supply. The achieved wideband delay is 10.6pS. Only 3% delay deviation over the 1–5 GHz band is observed, and this shows the excellent quality of the provided delay. The insertion loss is − 3.9 dB and is tolerable for a TTD cell. The input and output wideband impedance matching is ensured, and the S11 and S22 parameters are lower than -14.7 dB and − 10.9 dB, respectively. At last, the proposed TTD cell shows good linear performance, and IIP3 is around + 11.7 dBm.