Abstract
This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the T and the MTJ, either PMOS — bottom pin structure or NMOS — top pin structure can be a promising choice. Focusing on the PMOS–bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure’s effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90 nm CMOS/100 nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6 V. It will be an effective solution for 1T–1MTJ memories.
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