Abstract
In applications where signal frequencies are high, but information bandwidths are low, analog-to-information converters (AICs) have been proposed as a potential solution to overcome the resolution and performance limitations of high-speed analog-to-digital converters (ADCs). However, the hardware implementation of such systems has yet to be evaluated. This paper aims to fill this gap, by evaluating the impact of circuit impairments on performance limitations and energy cost of AICs. We point out that although the AIC architecture facilitates slower ADCs, the signal encoding, typically realized with a mixer-like circuit, still occurs at the Nyquist frequency of the input to avoid aliasing. We illustrate that the jitter and aperture of this mixing stage limit the achievable AIC resolution. In order to do so, we designed an end-to-end system evaluation framework for examining these limitations, as well as the relative energy-efficiency of AICs versus high-speed ADCs across the resolution, receiver gain and signal sparsity. The evaluation shows that the currently proposed AICs have no performance benefits over high-speed ADCs. However, AICs enable 2-10X in energy savings in low to moderate resolution (ENOB), low gain applications.
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