Abstract
A novel scaling limitation factor derived from DRAM retention time and its modeling has been proposed. So far, the well concentration has been optimized from the viewpoint of the scaling of the transistor dimensions. However, it has been found that the DRAM retention time strongly depends on the well concentration. Increase of the well concentration enhances thermionic field emission (TFE) current from the storage node. This leakage current makes tail distribution of the retention time. Therefore, the well concentration must be optimized taking into account the retention time distribution.
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