Abstract
This paper presents some examples of architectures for the implementation of wavelet codecs. Compared to previous works, the novelty of the approach is based on a joint optimization of both the algorithmic and architectural features, according to the overall system hardware and software strategy. The results of the analysis, although general for the different considered architectures, allow specific optimization of system performance for both dedicated ASIC design and embedded software implementation based on available system resources, such as execution speed and cache performance, while minimizing power consumption.
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