Abstract
Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications.
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