Virtual element method for thermomechanical analysis of electronic packaging structures with multi-scale features

A proof of concept of the Highly Accelerated Life Testing (HALT) technique was explored to assess and optimize electronic packaging designs for long duration deep space missions in a wide temperature range (–150°C to +125°C). HALT is a custom hybrid package suite of testing techniques using environments such as extreme temperatures and dynamic shock step processing from 0g up to 50g of acceleration. HALT testing used in this study implemented repetitive shock on the test vehicle components at various temperatures to precipitate workmanship and/or manufacturing defects to show the weak links of the designs. The purpose is to reduce the product development cycle time for improvements to the packaging design qualification. A test article was built using advanced electronic package designs and surface mount technology processes, which are considered useful for a variety of JPL and NASA projects, i.e. (surface mount packages such as ball grid arrays (BGA), plastic ball grid arrays (PBGA), very thin chip array ball grid array (CVBGA), quad flat-pack (QFP), micro-lead-frame (MLF) packages, several passive components, etc.). These packages were daisy-chained and independently monitored during the HALT test. The HALT technique was then implemented to predict reliability and assess survivability of these advanced packaging techniques for long duration deep space missions in much shorter test durations. Test articles were built using advanced electronic package designs that are considered useful in various NASA projects. All the advanced electronic packages were daisychained independently to monitor the continuity of the individual electronic packages. Continuity of the daisy chain packages was monitored during the HALT testing using a data logging system. We were able to test the boards up to 40g to 50g shock levels at temperatures ranging from +125°C to -150°C. The HALT system can deliver 50g shock levels at room temperature. Several tests were performed by subjecting the test boards to various g levels ranging from 5g to 50g, test durations of 10 minutes to 60 minutes, hot temperatures of up to +125°C and cold temperatures down to -150°C. During the HALT test, electrical continuity measurements of the PBGA package showed an open-circuit, whereas the BGA, MLF, and QFPs showed signs of small variations of electrical continuity measurements. The electrical continuity anomaly of the PBGA occurred in the test board within 12 hours of commencing the accelerated test. Similar test boards were assembled, thermal cycled independently from -150°C to +125°C and monitored for electrical continuity through each package design. The PBGA package on the test board showed an anomalous electrical continuity behavior after 959 thermal cycles. Each thermal cycle took around 2.33 hours, so that a total test time to failure of the PBGA was 2,237 hours (or ~3.1 months) due to thermal cycling alone. The accelerated technique (thermal cycling + shock) required only 12 hours to cause a failure in the PBGA electronic package. Compared to the thermal cycle only test, this was an acceleration of ~186 times (more than 2 orders of magnitude). This acceleration process can save significant time and resources for predicting the life of a package component in a given environment, assuming the failure mechanisms are similar in both the tests. Further studies are in progress to make systematic evaluations of the HALT technique on various other advanced electronic packaging components on the test board. With this information one will be able to estimate the number of mission thermal cycles to failure with a much shorter test program. Further studies are in progress to make systematic study of various components, constant temperature range for both the tests. Therefore, one can estimate the number of hours to fail in a given thermal and shock levels for a given test board physical properties.

Package delamination is a common problem in electronic packaging, and this study focused on the low-profile fine-pitch ball grid array (LFBGA) and plastic ball grid array (PBGA) package of composite and metal bonding and bonding mechanism to decrease the occurrence of delamination. In LFBGA, the physical and chemical properties were discussed by roughness and pure copper/nickel bonding experiment. In PBGA, delamination occurred between the corner of the heat sink and the epoxy resin, so the PBGA package process was simulated by the finite element method; moreover, the model was established and simulated by computer software ANSYS. The chip size, chip thickness and shoulder width were chosen as the parameters of response surface methodology (RSM). Finally, the results showed that the shoulder width has the greatest degree of influence on the stress concentration, and the shoulder width has negative correlation with stress value. In addition, the original design of the PBGA heat sink was changed, which the corner of the heat sink was changed to chamfer shape. From the results of the simulation, when the chamfer radius was larger, the stress value had decreased.

PurposeThe purpose of this paper is to develop a systematic experimental investigation for testing dynamic behavior of plastic ball grid array (PBGA) integrity in electronic packaging and to investigate the dynamic behavior of PBGA assembly by considering fixed‐modes for design and reliability evaluation of PBGA packaging.Design/methodology/approachA PBGA assembly prototype with different structure and material parameters is designed and manufactured. The modal distribution under excitation cycling can be tested by hammering test. The dynamic test about the PBGA assembly prototype can be implemented with different structure characteristics, materials parameters and fixed‐modes. To illustrate the validity of experimental test, the numerical simulation for the dynamic behavior of the PBGA assembly prototype is developed by using finite element method. Comparison between the experimental results and simulation can illustrate the validity of the experimental test and finite element modeling each other.FindingsThe modal distribution test shows the influence of structure characteristics, materials parameters and fixed‐modes of PBGA assembly board. The changing trends of the dynamic modal characteristics during the dynamic excitation can be obtained with different structure characteristics, materials parameters and fixed‐modes of PBGA assembly. Test shows that the fixed location of the assembly board is the most important factor to influence the first frequency and modal deformation of the assembly board. Higher frequency and smaller deformation can be obtained when there are more constraints in printed circuit board.Research limitations/implicationsThe numerical model is a compendious model by predigesting structure. The research on more accurate mathematical model of the PBGA assembly prototype is a future work.Practical implicationsIt can imply the dynamics of PBGA assembly. It builds a basis for future work for design and reliability evaluation of PBGA packaging.Originality/valueThis paper provides useful information about the dynamic behavior of PBGA assembly with different structure characteristics, materials parameters and fixed‐modes.

With the rapid progress in CMOS VLSI technology, feature size has decreased dramatically from 0.5 to 0.25 /spl mu/m, while chip drivers have become faster with sub-ns transitions. Most modern ICs work with a low power supply voltage with a low logic swing, and have widened their data bus from 16 to 32 or even 64 bits. All of these factors push modern packages toward greater pin counts, smaller form factors, and better electrical performance. As packages convey signals between ICs and act as inductance and capacitance components (at certain operating frequencies), packages with lower parasitic effects thus have better electrical performance. For high speed multi-function ICs, ball grid array (BGA) packages have increased their market share and thus have severe parasitic effect requirements. Simulations and measurements of electrical parasitics are crucial studies in the development of BGA packages and package selection for advanced ICs. In this paper, four types of BGA package, including 2-layer PBGA (plastic BGA), TEPBGA (thermally and electrically enhanced PBGA), FCPBGA (flip chip PBGA) and 4-layer PBGA, have been studied. The TEPBGA includes a heat slug as ground plane. All of the BGA packages are based on organic BT substrates. The paper describes: (a) the electrical simulation technique for each package, where realistic signal paths were analyzed and modeled; (b) the measurement method for each package. The results are summarized in terms of capacitance and inductance for each package, and both simulation and measurement data are presented.

There are continuous efforts in the electronics industry to reduce electronic package size. The main force pushing for smaller package size is the desire by original equipment manufacturers to reduce their mother board size and thereby their own cost. Reducing the size of electronic packages can be achieved by a variety of means and for ball grid array (BGA) packages an effective method is to decrease the pitch between the individual balls. Reducing the pitch between balls decreases the ball size and therefore the standoff between the packages and motherboards is reduced. The reduced standoff has the negative effect of reducing board-level reliability. An experiment to understand board-level reliability improvement by underfilling the BGA will be presented for several fine-pitch plastic BGA types (fleXBGA(R) and MAP (mold array process)). Four different (snap-cure) underfill epoxies with varied coefficients of thermal expansion and elastic moduli were used so that the preferred set of epoxy properties could be determined. A full factorial numerical experiment was used to identify the optimum combination of CTE and elastic modulus. Results indicate that a significant increase in board-level reliability can be achieved by underfilling the BGA.

Fine-pitch ball grid array (BGA) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive un- derhood environment is not well understood. In this work, the re- liability of fine-pitch plastic ball grid array (PBGA) packages has been evaluated in the automotive underhood environment. Exper- imental studies indicate that the coefficient of thermal expansion (CTE) as measured by thermomechanical analyzer (TMA) typi- cally starts to change at 10-15 C lower temperature than the specified by differential scanning calorimetry (DSC) potentially ex- tending the change in CTE well into the accelerated test envelope in the neighborhood of 125 C. High substrates with glass-tran- sition temperatures much higher than the 125 C high tempera- ture limit, are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the acceler- ated test. Darveaux's damage relationships (1)-(3) were derived on ceramic ball grid array (CBGA) assemblies, with predominantly solder mask defined (SMD) pads and 62Sn36Pb2Ag solder. In ad- dition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than the non solder mask defined (NSMD) pads in thermal fatigue. The thermal mismatch on CBGAs is much larger than PBGA assem- blies. Crack propagation in CBGAs is often observed predomi- nantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15, 17, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high- printed cir- cuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of bis-maleimide triazine (BT) substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants. Index Terms—Ball grid array (BGA), bis-maleimide triazine (BT), ceramic ball grid array (CBGA), coefficient of thermal expansion (CTE), non solder mask defined (NSMD), plastic ball grid array (PBGA), thermomechanical analyzer (TMA).

Ball Grid Array (BGA) packages have been gaining popularity due to the increasing demand for greater interconnect density. For high I/O applications, plastic BGA (PBGA) and tape BGA (TBGA) are attractive alternatives to fine-pitch quad flat pack and pin grid array packages because of their relative low cost, ease of surface mount assembly, and smaller board space requirement. However, since PBGA and TBGA are non-hermetic packages, they are vulnerable to moisture-induced damage during the surface mount assembly process. An evaluation was performed to investigate the impact of moisture on package delamination and cracking during the solder reflow process and the reliability of PBGA and TBGA packages. Based on our study using scanning acoustic microscopy and reliability stress tests, both PBGA and TBGA can be safely surface mounted if proper storage and handling guidelines are followed.

The application of Ball Grid Array (BGA) technology in electronic packaging on high I/O plastic and ceramic packages has grown significantly during the past few years. Although PBGA (plastic BGA) has several advantages over fine-pitch Quad Flat Pack (QFP) in terms of smaller package area, higher I/Os, lower switching noise, large pitch, higher assembly yield, and improved robustness in manufacturing process, potential package reliability problems can still occur, e.g., excessive solder joint deformation induced by substrate warpage, moisture ingression (popcorn effect), large variation in solder ball size, voiding as a result of flux entrapment and improper pad/solder mask design (Marrs and Olachea, 1994; Solberg, 1994; Freyman and Petrucci, 1995; Lau, 1995; Donlin, 1996; Lasky et al., 1996; Munroe et al., 1996). Regardless of its improved thermal fatigue performance over the past few years through an extensive amount of research, the BGA solder joint may still pose a reliability issue under harsh environment, e.g., automotive underhood, larger package size, or higher temperature and temperature gradient due to increase in power dissipation of the package. Numerous studies in BGA solder joint deformation and reliability under thermal and mechanical loadings can be found in the literature, e.g., Borgesen et al. (1993), Choi et al. (1993), Guo et al. (1993), Ju et al. (1994), Lau et al. (1994) Lau (1995), and Heinrich et al. (1995). Also, reliability prediction models have been developed by, e.g., Darveaux et al. (1995) and Darveaux (1996). The present study focuses on the application of a detailed nonlinear finite element analysis (FEA) to studying the thermal cyclic response of solder joints in two particular BGA packages, full-matrix and perimeter. Both time-independent plasticity and time-dependent effect, i.e., creep and relaxation, are considered in the constitutive equations of solder joint to evaluate the discrepancy in the results of life prediction. The critical solder joint is identified, and the locations that are most susceptible to fatigue failure in the critical joint are discussed. Some limitations in computation and reliability prediction are also discussed.

In this paper, some potential influencing factors of the TSV (Through Silicon Via) interposer were analyzed in high frequency bands from 10 GHz to 50 GHz by HFSS software. An interposer model with QFN (Quad Flat No-lead Package)-BGA (Ball Grid Array) transmission structure was designed to investigate the influence of the parameters such as shape, distance of BGA solder joint and TSV. In the model, TSV was used to connect QFN pad and BGA balls to transmit signal. According to the simulation results, the shape and distance of BGA balls significantly affect the RF transmission performance. A cylinder-shape BGA solder joint has better performance. In addition, the radius, distance and shape of TSV have obvious influence on the transmission performance of the interposer in the relative high frequency bands. The T-shape of TSV, short distance between RF TSV and GND TSV are both weak influencing factors.

In order to effectively acquire the comparable vibration degradation test data of interconnection structures in electronic packaging, problems which may exist in the reliability test of electronic packaging are analyzed in depth, using the existing environmental testing standards and combining with the accumulated experience in practical electronic reliability experiments. A complete set of degradation test methods for vibration failure of interconnected structures was proposed. This method can give a complete solution for the failure test of the interconnection structure in electronic packaging. Analysis of experimental data shows that the test data can well characterize the degradation process of the interconnected structures, and the outside interconnection structures in electronic packaging are easier to fail than the inside interconnection structures. The experimental method can effectively guide the implementation of the degradation test in the field of electronic interconnected structures in electronic packaging.

With the increasing of packaging density and functional diversity, electronic packaging structures with multiscale features have brought huge demand. To analyze elastoplastic problems of multiscale structures in electronic packaging, this paper presents an efficient coupling scheme of Abaqus and a self-written boundary element method (BEM) code. In the numerical analysis, based on the geometric features of the multiscale structures, the whole domain is divided into two domains: FE domain and BE domain. The Abaqus is used in the FE domain where non-linear or nonhomogeneous behavior is expected, whereas the linear elastic domain or large-scale domain is solved by the BEM code. The BE part in the whole FE-BE model is defined as a super element (user-defined element in Abaqus) of the FE, and its effective stiffness and effective nodal forces at the interfacial boundary are evaluated by the BEM code and assembled by the user subroutine (UEL) into the FE system. Users not only benefit from the powerful functions of Abaqus, but also can use BEM as a complement to improve solution accuracy. The numerical example shows that the stress results obtained by the scheme are in a great agreement with the results obtained by a detailed finite element model.

This work compared ball grid array (BGA) lead-free solder joint strengths to eutectic lead (Sn–Pb) solder joint strengths under monotonic bend load at room temperature. Flexural test methodologies for evaluating solder joint strength are presented. Various effects on solder joint strength were summarized systematically into three parts. The first part focused on the effect of solder joint geometries. BGAs with Sn-4Ag-0.5Cu and 63Sn-37Pb solders were tested, respectively. The effects of package side solder resist opening sizes, solder ball diameters, and board side metal defined/solder mask defined pads were investigated with 0.062 in printed circuit board (PCB). The results showed that the solder joint strength of Sn–Ag–Cu solder is lower than that of the traditional Sn–Pb solder under room temperature board flexural load and similar dynamic load. The second part investigated the effects of type of package (plastic BGA (PBGA) versus ceramic BGA (CBGA)), board thickness (0.093 in. versus 0.135 in.), and the effect of rework (reworked versus non-reworked) with Sn-3.9Ag-0.7Cu and 63Sn-37Pb solders. The joint strength of Sn–Ag–Cu solder is consistently lower than that of eutectic Sn–Pb solder for both board thicknesses, both CBGA and PBGA packages, and both non-reworked and reworked packages. The third part explored the feasibility of alternative low temperature solders as board-level interconnects. In addition to the traditional 63Sn-37Pb solder and the lead-free Sn-4Ag-0.5Cu solder, four other lead-free solders (Sn-52In, Sn-58Bi, Sn-57Bi-1Ag, and Sn-9Zn-0.006Al) were tested with 0.044 in PCB. Effects of board surface finishes with immersion silver (ImAg) or organic solderability preservatives, and pads with via-in-pad (VIP) or non-VIP pads were investigated. Test results showed that most of the BGAs with non-VIP pads performed better than those with VIP pads, except Sn–In solder with ImAg surface finish. The Sn–In solder showed the lowest performance, while Sn–Bi and Sn–Bi–Ag solder compositions showed better performance. Sn–Zn–Al solder joint strength performs better than others.

The paper (1) experimentally determines the survivability/durability of the solder joints of ball grid array (BGA) with/without under-filled materials when subjected to military vibration environment and (2) develops a vibration fatigue life prediction model, which is qualitatively calibrated by test. A test vehicle (TV), on which various sizes of BGA daisy-chained packages with/without under-filled materials, e.g., Hysol (non-reworkable) and Hacthane (reworkable) are soldered, is first designed, fabricated and subjected to random vibration tests continuously monitoring the solder joint integrity. Based on the measurement results, a destructive physical analysis is then conducted to further verify the failure locations and crack paths of the solder joints. Test results indicate that: (1) ceramic BGA (CBGA) mounted to the same modules will be more susceptible to failure than, the plastic BGA (PBGA) under the same conditions; (2) the PBGA solder joint fatigue life could be increased by one-order-of-magnitude (or more) using either one of under-filled materials in the packages versus using no underfilled material; (3) the use of under-filled material of Hysol could also improve the life expectancy of the CBGA by more than a factor of ten; and (4) only a slight increase in the life of the CBGA with using the under-filled material of Hacthane.

Mechanical properties of Sn–Pb based solder joints and fatigue life prediction of PBGA package structure

The objectives of the present studies are to design and test representative commercial off-the-shelf plastic encapsulated microcircuits, including various types of ball grid array (BGA) components, chip scale package, flip chip, lead flat pack, and leadless capacitor, over military random vibration levels. The approach is to demonstrate the solder joint reliability performance of these components through the design of an electrical daisy-chain pattern printed wiring board (PWB) assembly test vehicle (TV), in which the design and manufacturing variables are included. The three variables, including BGA underfilled materials, solder pad sizes on PWB, and BGA rework, with each having either two or three levels of variation are used to address test criteria and to construct 14 different types of TV configurations. All TV configurations are then subjected to random vibration tests while continuously monitoring solder joint integrity. Based on the measured results, a destructive physical analysis is then conducted to further isolate the failure locations and determine the failure mechanisms of the solder joints. Test results indicate that the 352-pin tape BGA and 600-pin super BGA are more susceptible to failure than plastic BGAs under the same conditions, and that the use of underfilled materials appears to improve the life expectancy of all the components. The stiffer packages of tape BGA and super BGA, which have copper heat spreaders, may account for higher BGA solder joint stress/strain during random vibration tests. Test data also shows that only a limited number of electrical opening are observed. This indicates that the test modules are robust enough to survive the random vibration inputs. One possible reason is that the test modules are very stiff, whose 1st mode of natural frequency is about 550 Hz. Therefore, the curvature changes of the test modules are minimal, which resulted in smaller relative motion between the package and the PWB, and less solder joint stresses. All these test results are recommended to be used for calibrating BGA solder joint vibration fatigue life prediction models, which will be presented in other publications.