Abstract
Conventional techniques for automatically verifying liveness properties of circuits involve explicitly modeling infinite behaviors with either infinite paths through a Kripke structure or with strings in an ω-regular language. This paper describes how timed trace structures [2, 3] can be used to convert liveness properties (including unbounded liveness properties such as strong fairness) to safety properties. Such properties can then be modeled and verified using only finite traces. No new algorithms are needed. All that is required is a new interpretation of what behaviors are represented by the finite traces. A mapping is defined between timed trace structures and complete trace structures [5], which contain infinite traces, to show that this new interpretation makes sense. The method is demonstrated on a fair mutual exclusion circuit.
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