Verification of Sequential Circuits

Abstract

The problem of verifying the equivalence of two implementations of a sequential circuit and the problem of test generation for such circuits axe intimately related. The verification problem can be formulated as a decision problem where given two descriptions of a circuit, the question asked is whether the two descriptions have the same functionality. With the increasing use of sophisticated, automatic optimization tools in the synthesis of combinational and sequential logic circuits, it has become essential to be able to efficiently verify that the optimized and original descriptions represent the same machine, i.e., the synthesis process has not introduced any errors in the circuit. As observed in Chapter 1, verification is required at all stages of the design process and different verification techniques are used at different stages for verification. One of the most important phases of the design process is sequential logic optimization. At this level, various techniques like retiming [79, 86], decomposition [7], optimization under don’t-cares [38, 80], and re-encoding [38] are used to transform the logic-level description of the circuit to a more optimal description. The focus of this chapter is the verification of circuits described at the logic level. The main application of the techniques described in this chapter is in verifying the correctness of the optimization and synthesis tools.