Verification and Validation of Standard Cell Scan C-element in Prototype Chip

Asynchronous circuits are attracting attention because they can provide solutions to clock-skew and power dissipation problems of synchronous circuits. On the other hand, asynchronous circuits are more complex than synchronous circuits, and so formal verification becomes an essential step in the asynchronous circuit design. In this paper, we propose an approach to the formal verification of asynchronous circuits based on process algebra. In our approach, we describe both the asynchronous circuit and its specification using process expressions, and check the correctness of the circuit with respect to the specification by constructing the parallel composition of those processes. The advantages of this approach are that the descriptions are easily readable and that the method is fully automatic. Further, we propose a simple algorithm to check the restricted liveness properties of circuits. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(8): 33–43, 1997

Asynchronous circuit designs have shown great promise for overcoming synchronous timing overhead and power requirements of functionally equivalent, continuously-clocked circuit designs. In some instances, such as memory data path applications, speed independent, asynchronous pipelines are used to provide low-latency, high-throughput logic paths. Asynchronous pipelines use local handshaking to avoid the problems of clock skew, switching noise and switching power generated by global clock distributions found in synchronous circuit designs. Asynchronous pipelines that exhibit the property of speed independence provide functional tolerance to low supply voltage, and are modular in application, given proper adherence to interface protocol. The advantages of asynchronous circuits, relative to synchronous circuits, are not without cost. Asynchronous circuits can pose difficulties with testing, interfacing to synchronous environments, and a general lack of well-established, industry standard design and verification tools, which often forces asynchronous designs to be realized using full-custom design methodologies. This tutorial will present recent developments in the literature related to asynchronous pipeline protocols and circuits. Unique circuit constructs and applications will be presented with emphasis on interfacing asynchronous circuits to synchronous environments, controlling dynamic logic paths, and applications that call for the flexibility of varying forward path, inter-stage cycle times within an asynchronous logic pipeline.

Traditionally, synchronous sequential circuits are considered controlled by input pulses, and asynchronous sequential circuits by input levels. The aim of this note is to study the general properties of a class of asynchronous circuits with some inputs that can be thought of as driven by "pulses." The synthesis process and the internal structure of these circuits, called pulse input asynchronous sequential circuits (PA circuits), are investigated, and they are compared with pulse input synchronous circuits and with level input asynchronous circuits. Procedures are described to transform any flow table describing a synchronous circuit into a flow table describing an equivalent PA circuit, and to realize any normal mode asynchronous circuit by a PA circuit. Specific techniques for PA circuit state reduction and PA circuit state assignment are described in other papers.

Compared with common bus system, GALS (Global Asynchronous Locally Synchronous) bus system can combine the respective advantages of synchronous circuits and asynchronous circuits, and is trend of System-on-Chip design. However, different data encodings are applied in synchronous circuits and asynchronous circuits, which makes it impossible to achieve the cooperation of synchronous modules and asynchronous modules, thus synchronous and asynchronous packaging circuits become the research focus in GALS(globally asynchronous locally synchronous) bus systems. In this paper, a synchronous and asynchronous packaging circuit under four-phase one-hot encoding is designed based on the standard gates. Verifications of the packaging circuit are implemented on Xilinx Viretex5 of 65nm CMOS technology. The results show that the power is reduced by 58.3%, the working speed of synchronous-to-asynchronous module increased by 54.6%, and the working speed of asynchronous-to-synchronous module increased by 64.7% compared with the traditional suspended clock packaging circuits.

The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4×4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.

As a result of advances in technology shrinking device dimensions, the occurrence of transient errors is increasing. This together with the concomitant reduction in supply voltages has decreased noise margins causing system reliability to be reduced, at a time when electronic systems are being used increasingly in 'safety critical' applications. Previous work has demonstrated that an information redundant Concurrent Error Detection (CED) scheme using Dong's Code can be applied efficiently to a processor using an asynchronous design style incurring area overheads of approximately 12% [1] when placed on silicon. This paper furthers the above work by extending the capabilities of the processor to include the multiplication function also guarded by a CED scheme, permitting the processor to be used in a wider range of applications; e.g. DSP. The paper also demonstrates that a reduction in power of 22% can be achieved by utilising an asynchronous design style rather than its synchronous counterpart. Furthermore, the power overhead for the asynchronous CED processor was found to be 5% less than that of the synchronous processor without CED. Asynchronous design style is also known to have the inherent benefit of not requiring difficult to design, global timing clock trees and networks. Previous work has also demonstrated that approximately, 25% area savings can be made when comparing Dong's Code to a Berger Code CED scheme on the multiplier function [2]. Through the implementation of a larger number of operations within the ALU, all protected by the same information redundant code, further savings can be made through reuse of common blocks, as codes often share many similarities within their prediction equations. With lower power dissipation and a reduced area overhead, compared to its synchronous counterpart, this makes the asynchronous CED circuit attractive and viable for reliable mobile computation. This paper also extends the work with the implementation of a synchronous and asynchronous processor, with and without CED on a FPGA.

FPGA device is a dominant implementation medium for digital circuits. Unfortunately, they do not support asynchronous circuits because of the lack of asynchronous circuit elements such as Muller gates, etc. In this paper, new efficient approaches are proposed to prototype asynchronous or mixed synchronous/ asynchronous circuits on look-up table-based (LUT) FPGA rapidly. The developed techniques are based on building of elements which play an important role in asynchronous circuits. The hazard-free elements are predefined in libraries in HDL and EDIF format. Timing and/or area constraints for place&route tool are automatically generated to map the asynchronous elements on suitable FPGA's logic blocks. Several FPGA devices such as Altera, Xilinx and Actel could be used as target for the implementation. For the purpose of demonstration, some asynchronous circuits are implemented with Xilinx Spartan 3 FPGA family.

In this paper a new scan design for detection of stuck-at faults and delay faults in asynchronous sequential circuits based on the micropipeline approach is proposed. This new scan methodology can gain the high fault coverage of path delay fault as well as stuck-at fault with the small area overhead in the asynchronous micropipeline environments and easily expand the application such as built-in self testing.

There are three well-known approaches to using scan design to apply two-pattern testing: broadside testing (functional justification), skewed-load testing and enhanced scan testing. The broadside and skewed-load testing use the standard scan design, and thus the area overheads are not high. However fault coverage is low. The enhanced scan testing uses the enhanced scan design. The design uses extra latches, and allows scan-in any two-pattern testing. While this method achieves high fault coverage, it causes high area overhead because of extra latches. This paper presents a new scan design where two-pattern testing with high fault coverage can be performed with area overhead as low as the standard scan design. The proposed scan-FFs are based on master-slave FFs. The input of each scan-FF is connected to the output of the master latch and not the slave latch of the previous FF. Every scan-FF maintains the output value during scan-shift operations.

This work proposes automatic test pattern generation (ATPG) for Null Convention Logic (NCL). NCL is a robust asynchronous paradigm that introduces new challenges to test and testability algorithms due to the lack of a clock signal and the presence of a large number of state holding elements. The main features of this work are clockless, self-timed ATPG for all single stuck-at faults in NCL circuits, including those of gate internal feedback (GIF). The detection of faults on GIF is performed with no added test hardware. To the extent of our knowledge, this is the first work which has addressed clockless, self-timed ATPG with coverage for faults on GIF of NCL gates and with no area overhead. The proposed test generation algorithms are evaluated for several real-size NCL circuits with average 96.2% fault coverage.

Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IDDQ</sub> (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clockless, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDQ</sub> test for NCL.

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-for-testability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.

Modern asynchronous digital circuits are highly concurrent systems composed largely of customized gates, and can be elegantly modeled using the language of production rules (PRs). One of the present limitations of the state of the art in asynchronous circuit design is that no formal executable semantics of asynchronous circuits has yet been given at the PR level. The primary contribution of this paper is to define, using rewriting logic and Maude, an executable formal semantics of asynchronous circuits at the PR level under three common timing assumptions. Our semantics provides a circuit designer with a PR-level circuit interpreter and with a decision procedure for checking key circuit properties, including hazard-freedom and deadlock-freedom. We describe several reductions and optimizations that can be used to reduce the state space of circuits in our formal semantics and investigate the impact of these reductions experimentally. The analysis scales up to circuits of over 100 PRs in spite of the high levels of concurrency involved.

The purpose of this book is to present a current view of the state of the art for the field of asynchronous circuit design and analysis which was the topic of a workshop in Banff in the fall of 1993. Asynchronous circuits have been studied in one form or another since the early 1950’s [64] when the focus was primarily on mechanical relay circuits and when the differences between the asynchronous and clocked circuit design styles were somewhat indistinct. A number of theoretical issues were studied in detail by Muller and Bartky as early as 1956 [92]. Since then, the field of asynchronous circuits has gone through a number of high-interest cycles. In the last 5 years there has been an unprecedented level of interest in both academic and industrial settings [56]. This historical trend continues today with the majority of the current research effort focused more on theory than on practice. Nonetheless, the advance of practical asynchronous circuit design techniques also has an unusual level of interest. The work presented at the Banff workshop was concerned more with practice than theory and provided a reasonable coverage of the current approaches to asynchronous circuit design. Similarly this chapter will primarily focus on practical design issues. Prior to introducing the four chapters which follow, we present an introduction to the basic concepts and motivations behind asynchronous circuit design. This will hopefully enable those not already familiar with asynchronous circuit design to better understand the subsequent chapters.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.