Validation of wire length distribution models on commercial designs

Abstract

In advanced integrated circuits (IC's), the wires interconnecting active devices will increasingly affect IC performance, manufacturability and reliability. Predictions for microprocessors indicate that the amount of wiring required to interconnect the rapidly increasing number of transistors will rise from about 11 km, distributed over 6 to 7 metal layers, for the current 180 nm technology node to as much as 150 km, in 10 metal layers, for the 30 nm node [1]. This vast increase of wiring demand, together with the projected decrease in wiring pitches, strongly affects IC manufacturability (e.g. routability and yield) and reliability (electromigration and enhanced device stress). Electrical performance issues (delay, power dissipation, and noise) also become dominated by the lengthy and dense interconnect wires and it will become a real challenge to meet IC design targets.At present, many developments are on-going in IC process technology, design styles and CAD tooling to cope with the limitations posed by the interconnect. The renewed interest in the modeling of wire length distributions prior to layout [2], which builds upon the early work of Donath from 1979 [3], offers possibilities in guiding these developments. For example, the advantages of incorporating new materials in the backend process can be weighted against the (considerable) integration efforts, or the effects of different scaling scenarios for the interconnect tiers can be assessed. In the development of standard cell libraries, the influence of cell dimensions on the routing resources can be considered. During physical design, direct feedback can be provided on the wiring demand for a particular design, useful for example to get a (fast) indication whether it will be feasible to place that design on a certain floorplan size and shape. Other applications can be thought of, involving CAD tools or new interconnect (3D-) architectures [4]. In general, the applicability of wire length distribution models will strongly depend on their level of accuracy.Within Philips Research, the accuracies of current wire length distribution models have been assessed for a series of benchmark circuits. The model approach of Davis [5] is followed which, like other model approaches, is based on Rent's Rule [6] and simplifies matters by assuming that circuits consist of identical (homogeneous) cells. It will be shown that the application of Rent's Rule, relating the number of terminals required for outside communication to the number of cells inside a given partition, yields significant underestimations of wire length distributions and that inclusion of the floorplan boundaries, as done in a recently-published extension of Rent's Rule [7], is required to improve matters. The homogeneity assumption will be addressed, as well as the trade-off between numerical and analytical models. Future model and application challenges will be put forward for discussion.