Use of optical AEI metrology to compute overlay and etch-induced tilt in logic

Abstract

In advanced logic nodes, edge placement error (EPE) budget becomes tighter. Such budget needs to account for items that were nearly negligible before FinFET era, such as rule-based etch bias error or overlay metrology to device (MTD) bias. Some of the new challenges are overlay metrology error due to process induced mark asymmetry, after Etch Inspection (AEI) pattern shift and aberration induced overlay difference between mark and device, all summarized as Metrology to Device bias. YieldStar In-Device Metrology (YS IDM) addresses device-like metrology and real AEI overlay, but in principle might suffer from process asymmetry. In this work we measure ASML Self Reference (ASR) targets by IDM. We use the detected IDM signal to quantify and address for the first time the asymmetry of the printed marks containing device-like structures on FEOL with respect to reference tool. Two main findings characterize this work: - IDM has the capability to identify overlay and tilt signal from a multi-wavelength signal. Scanning electron microscopy (SEM) is a different metrology tool which, to our best knowledge, is instead detecting the two signals as one, without separating them. Overlay and tilt signals identified by IDM can be combined in order to match to SEM - The relative amount of overlay and tilt carried by the IDM signal shows a monotonic and continuous wavelength dependency. These findings increase the understanding of the delta IDM to SEM method, improving the matching between the two. The separation of overly and tilt allows to distinguish which part of the process is causing a certain fingerprint, as tilt is purely driven by non-litho processes. In addition, the combination of overlay and tilt metrology allows improved correlation of the detected AEI signal to yield, and the definition of KPIs for smaller MTD fingerprint. Finally, IDM provides the possibility to keep throughput benefits of optical metrology while overcoming the robustness challenges