Abstract
The design of the power management logic (PML) of complex low-power system-on-chip (SoC) designs is rooted in the expected workload patterns in the target architecture. The increasing functionality of SoCs is complimented by increasingly diverse usage patterns among its users, leading to a situation where the same device is power efficient for some user and power inefficient for others. This letter positions the potential benefits of personalizing the PML in SoCs leveraging that the global power management strategy resides in firmware.
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