Abstract
URPR-1 is a VLIW architecture which integrates nine PEs on a single chip. It adopts a pipeline register file to eliminate the data anti-dependencies in the innermost loops of the program, thereby further exploiting the instruction-level parallelism and increasing the execution speed of loops. The results of preliminary evaluation on simulators show URPR-1 architecture to have high performance. This paper first introduces the architecture of URPR-1 and its optimizing compiler, and presents the basic principle of pipeline register file; then gives some representative examples to demonstrate the working procedure of URPR-1 and its compiler, and the results of preliminary experiments.
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