Abstract
An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.
Highlights
Due to the rapid development of semiconductor process capabilities, the progress rate of the future process has become unpredictable
According to an update to the International Technology Roadmap for Semiconductors (ITRS), manufacturing speed and testing progress will significantly change in the future, with product manufacturability increasing by 30% annually and testing abilities rising by 12% annually [5,6,7]
This indicates that testing capabilities have not kept up with the capabilities of the semiconductor manufacturing technology
Summary
Due to the rapid development of semiconductor process capabilities, the progress rate of the future process has become unpredictable. According to an update to the International Technology Roadmap for Semiconductors (ITRS), manufacturing speed and testing progress will significantly change in the future, with product manufacturability increasing by 30% annually and testing abilities rising by 12% annually [5,6,7]. Owing to uncertain factors in a semiconductor manufacturing environment, the electrical characteristics of a product are shifted during a manufacturing process; the electrical properties of each produced chip are different. Due to uncertainty factors in the manufacturing environment (mask error, etching and chemical concentration errors) after manufacturing, we assume the chip delay time of a device under test (DUT) is normal. The parameters include product manufacturability (Pm), which is expressed asand as temperature and exposure errors, chemical concentration errors during etching, the shifting of the electrical properties of components.
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