Abstract
An ultra-low voltage sixth-order low pass filter topology, suitable for sensing the T-wave signal in an electrocardiogram (ECG), is presented in this paper. This is realized using a cascade connection of second-order building blocks constructed from a sinh-domain two-integrator loop. The performance of the filter has been evaluated using the Cadence Analog Design Environment and the design kit provided by the Austria Mikro Systeme (AMS) 0.35-µm CMOS process. The power consumption of filters was 7.21 nW, while a total harmonic distortion (THD) level of 4% was observed for an input signal of 220 pA. The RMS value of the input referred noise was 0.43 pA, and the simulated value of the dynamic range (DR) was 51.1 dB. A comparison with already published counterparts shows that the proposed topology offers the benefits of 0.5-V supply voltage operation and significantly improved power efficiency.
Highlights
Many physical conditions and diseases of the heart can be non-invasively detected through feature extraction from ECG
A sixth-order low pass filter topology is presented in this paper, realized using the concept of sinh-domain filtering
A value of dynamic range (DR) equal to 51.1 dB has been achieved under this ultra-low voltage environment, and according to the provided comparison results, the proposed topology offers the most power-efficient realization among the filters under consideration
Summary
In order to sense the T-wave, a low pass filter with a cutoff frequency of 2.4 Hz should be realized. The scheme in [4] has been realized using the concept of sinh-domain filtering, and the large signal characteristic of transistors has been used for the realization of time constants without the requirement of extra linearization stages. A sixth-order low pass filter topology is presented in this paper, realized using the concept of sinh-domain filtering. A value of dynamic range (DR) equal to 51.1 dB has been achieved under this ultra-low voltage environment, and according to the provided comparison results, the proposed topology offers the most power-efficient realization among the filters under consideration. Environment and MOS transistor models provided by the AMS C35 0.35-μm CMOS process
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