Twin tub III - A third generation CMOS technology

Abstract

A third generation Twin-Tub (1, 2) CMOS Technology was developed using 1.75 µm lines/spaces and epitaxial substrates to suppress latch-up. The 5.0 volt transistor structures use a 250 A gate oxide, polycide gates, 0.55 µm X j and 1.3 µm nominal channel lengths, n- and p-channel thresholds of 0.7 and -1.0 volts are obtained with a blanket boron ion implant. Long channel behavior and minimal threshold changes are obtained at geometries down to 0.9 µm channel length and 1.5 µm channel width. The time for linear threshold drift of 100 mv change extrapolates to > 1E5 hours for Vd < 5.5 V. This technology has been applied to the fabrication of the WETM32100 microprocessor and memory management chips (3, 4) and SRAM devices.