Abstract
The electrical performance of SiC-based microelectronic devices is strongly affected by the densities of interfacial traps introduced by the chemical and structural changes at the SiO2∕SiC interface during processing. We analyzed the structure and chemistry of this interface for the thermally grown SiO2∕4H-SiC heterostructure using high-resolution transmission electron microscopy (TEM), Z-contrast scanning TEM, and spatially resolved electron energy-loss spectroscopy. The analyses revealed the presence of distinct layers, several nanometers thick, on each side of the interface; additionally, partial amorphization of the top SiC surface was observed. These interfacial layers were attributed to the formation of a ternary Si–C–O phase during thermal oxidation.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
