Abstract
Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
