Towards reconfigurable optoelectronic hardware accelerator for reservoir computing

Abstract

Reservoir Computing (RC) is a subset of Recurrent Neural Networks (RNN) and has emerged as a powerful method for large scale classification and prediction of temporal problems with a reduced training time. Silicon-Photonics architectures have enabled high speed hardware implementations of Reservoir Computing (RC). With a Delayed Feedback Reservoir (DFR) model, only one non-linear node can be used to perform RC. In literature, multi-layer photonic RC architectures have been proposed by stacking multiple reservoirs together. Such architectures have demonstrated improved performance over single reservoir networks. However, as we show in the paper, for each task, the performance improvements saturate with a different number of layers. Hence, a hardware accelerator with fixed number of reservoir layers is not optimal for all tasks. Moreover, the gain in performance also comes at the cost of increased power consumption. Therefore, in this paper we propose a new reconfigurable optoelectronic architecture for multi-layer RC. Our proposed architecture, is based on DFR model implemented by the use of Mach Zehnder Modulator (MZM) and on chip low loss delay lines for improved performance. It integrates photonic switches based on Micro Ring Resonators (MRR) to enable reconfigurability. The architecture enables layer selection and layer gating to select the number of layers required for a task. Selection of number of layers can optimize the architecture for a specific application, resulting in huge power savings, while maintaining the overall accuracy. Our experiments with NARMA task and analog speech recognition task show that by optimally configuring an up-to 4-layer architecture, power savings up to 40% can be achieved compared to state-of-the-art architectures while gaining up to 80% more accuracy. Our scalable architecture has an on-chip area overhead of 0.0184mm2 for a single delay line and MRR switch.