Towards Perfection in Large Area, High-Resolution SEM for Integrated Circuit Reverse Engineering

Abstract

Abstract For large area, high resolution SEM imaging applications, such as integrated circuit (IC) reverse engineering and connectomics [1-3], SEM instruments are limited by small, uncalibrated fields of view (FOVs) and imprecise sample positioning. These limitations affect image capture throughput, requiring more stage drive time and larger image overlaps. Furthermore, these instrument limitations introduce stitching errors in 4 dimensions of the image data, X, Y, Z and I (signal intensity). Throughput and stitching errors are cited challenges [2] and software alone cannot tenably correct stitching errors in large image datasets [3]. Furthermore, software corrections can introduce additional errors into the image data via the scaling, rotation, and twisting of the images. So software has proven insufficient for reverse engineering of modern integrated circuits. Our methodology addresses the challenges brought on by small, uncalibrated FOVs and imprecise sample positioning by combining the resolution and flexibility of the SEM instrument with the accuracy (of the order 10 nm), stability, and automation of the electron beam lithography (EBL) instrument. With its unique combination of high resolution SEM imaging (up to 50,000 pixels x 50,000 pixels for each image), laser interferometer stage positioning, and FOV mapping, the reverse engineering scanning electron microscope (RE-SEM) produces the most accurate large area, high resolution images directly acquired by an SEM instrument [4]. Since the absolute position of each pixel is known ultimately to the accuracy afforded by the laser interferometer stage, these images can be stacked (3D-stitched) with the highest possible accuracy. Thus, the RE-SEM has been used to successfully reconstruct a current PC-CPU at the 22 nm node.