Towards a “Synchronous Reactive” UML profile?

Abstract

The domain of Real-Time Embedded (RTE) systems was ackowledged as being largely influential on many feature additions to the recent UML2.0 standard [Bjorkander, M., FDL'03 Keynote address, 2003]. Work on UML1.4 Scheduling, Performance & Time (SPT) profile also goes in that direction. Still, the paradigms underlying these modeling efforts are that of software components, running on a real-time OSs with physical time constraints and middleware (e.g., RT-Corba) concerns. In other areas of Embedded System Design other paradigms are at work, owing to codesign techniques at the border between software and hardware, or discrete time mathematical engineering (MATLAB/Simulink) and digital signal processing algorithms, etc. The paradigm of Synchronous Reactive (S/R) systems [Benveniste, A., Berry, G.: The synchronous approach to reactive and real-time systems. Proc. IEEE 79(9), 1270–1282 (1991); Benveniste, A., Caspi, P., Edwards, S., Halbwachs, N., Guernic, P.L., de Simone, R.: Synchronous languages twelve years later. Proc. IEEE 91(1), 64–83 (2003)], with discrete logical time and behavior decomposition into instantaneous reactions, proved quite natural in such areas to model mixed hardware/software System-Level Design (SLD). We describe here some of the modeling paradigms needed for a true S/R model framework, and corresponding diagrammatic interpretations. The synchronous reactive domain described here should be dealt with and included in the forthcoming UML profile for “Modeling and Analysis of Real-Time and Embedded systems” (MARTE), whose request for proposal was recently voted at OMG.