Towards a Robust Design of Electronics Assemblies under Fracture, Delamination and Fatigue Aspects

Abstract

Design studies of electronic components on the basis of parameterized FE-models and DoE/RSM-approaches are more and more performed to optimize it at early phases of the product development process. That is why electronics components especially in the field of RF, optoelectronics, high temperature and power applications are often exposed to extreme thermal environmental conditions, mechanical shock and vibrations. Simultaneously, the well known thermal expansion mismatch problem of the several materials, residual stresses generated by several steps of the manufacturing process and various kinds of inhomogeneity attribute to interface delamination, chip cracking and fatigue of interconnects, in particular. The applied methodologies typically base on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches. Recent studies show also how the evaluation of mixed mode interface delamination phenomena, classical strength hypotheses along with fracture mechanics approaches and thermal fatigue estimation of solder joints can simultaneously be taken into account. Here such an integrated approach is coupled with optimization algorithms towards a thermo-mechanical reliable design. At the same time, the attention is also turned to reach robustness against scattering model parameters - scattering of geometry as well as of materials properties, in particular. This leads directly to the consequence that all results show also scattering characteristics. The paper explains the methodology and results towards a robust design, to emphasize the potential of the utilized approach. Exemplarily, an underfilled flip-chip assembly based on reflow soldering and a non-underfilled flip-chip assembly with thermo-compression bonded metal-metal interconnections on low-k will be examined with regard to their board level reliability and robustness.