Top-down designs of instruction systolic arrays for polynomial interpolation and evaluation

Abstract

This paper describes the application of a new parallel architecture—Instruction systolic array (ISA)-for the interpolation and evaluation of polynomials using a linear array of processors. It also demonstrates a systematic top-down design of instruction systolic arrays. The periods of the resulting algorithms are O( n) for interpolation and O(1) for evaluation, where n is the degree of the polynomial.