Abstract
The transition from finFETs to nanosheet transistors is on. The industry is therefore looking into the options for a subsequent device, among which forksheet transistors appear as a serious contender [1]. Common to the processing of these Gate-All-Around architectures, the cavity etch, wherein SiGe is etched laterally from a SiGe/Si multilayer, remains a step of paramount importance [2]. Its development therefore requires new techniques for geometrical and material characterization. In this paper, we elaborate on the use of top-down spectroscopic techniques [3] to measure critical parameters such as cavity depth, stress and SiGe residues in nanosheet and forksheet transistors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
