Top-Down Approach: Fabrication of Silicon Nanowires using Scanning Electron Microscope based Electron Beam Lithography Method and Inductively Coupled Plasma-Reactive Ion Etching

A simple method for the fabrication of silicon nanowires using Electron Beam Lithography (EBL) combined with thermal oxidation size reduction method is presented. EBL is used to define the initial silicon nanowires of dimensions approximately 100 nm. Size-reduction method is employed for reaching true nanoscale of dimensions approximately 20 nm. Dry oxidation of silicon is well investigated process for self-limited size-reduction of silicon nanowires. In this paper, successful size reduction of silicon nanowires is presented and surface topography characterizations using Atomic Force Microscopy (AFM) are reported.

T-Gate fabrication processes for InP-based High electron mobility transistors (HEMTs) are described using PMMA/Al/UVIII. The single-step and two-step Electron beam lithography (EBL) methods are proposed contrastively without dielectric support layer. The opti- mal gate-foot length is 196nm for 50nm geometry path by single-step EBL technique. Since the gate-foot and gate-head are defined independently, the two-step EBL process minimizes forward scattering and enables smaller gate-foot length, which improves to be 141nm for 50nm geometry path and also 88nm for 30nm geometry path. Both EBL methods have been incorporated into InP- based HEMTs fabrication. With the gate-foot length de- creases from 196nm to 141nm, the current-gain cutoff fre- quency (fT) is improved from 125GHz to 164GHz, and also the maximum oscillation frequency (fmax )i ncreases from 305GHz to 375GHz.

Since the photoelectric response and charge carriers transport can be influenced greatly by the density and spacing of the ZnO nanorod arrays, controlling of these geometric parameters precisely is highly desirable but rather challenging in practice. Here, we fabricated patterned ZnO nanorod arrays with different densities and spacing distances on silicon (Si) substrate by electron beam lithography (EBL) method combined with the subsequent hydrothermal reaction process. By using the EBL method, patterned ZnO seed layers with different areas and spacing distances were obtained firstly. ZnO nanorod arrays with different densities and various morphologies were obtained by the subsequent hydrothermal growth process. The combination of EBL and hydrothermal growth process was very attractive and could make us control the geometric parameters of ZnO nanorod arrays expediently. Finally, the vertical transport properties of the patterned ZnO nanorod arrays were investigated through the microprobe station equipment, and the I-V measurement results indicated that the back-to-back Schottky contacts with different barrier heights were formed in dark conditions. Under UV light illumination, the patterned ZnO nanorod arrays showed a high UV light sensitivity, and the response ratio was about 104. The controllable fabrication of patterned ZnO nanorod arrays and understanding their photoelectric transport properties were helpful to improve the performance of nanodevices based on them.

Fabrication of Silicon nanowires (SiNWs) by electroless etching of p-type (100) Silicon wafer using silver (Ag) particles as catalyst at room temperature has been reported in this paper. Dependence of SiNWs formation on Ag electroplating and etching time was investigated. Surface morphology of SiNWs has been studied using scanning electron microscope (SEM) for different samples. The length of SiNWs increased with time of etching and decreased with electroplating time. A systematic study regarding the surface topography of fabricated SiNWs was performed using atomic force microscope (AFM). A 3D profile of the surface on a nanoscale were analysed and compared with SEM images. The average diameter of 73.9 nm for SiNWs was measured using as-obtained AFM images. Electroplating and etching time had minimum effect on the diameter of as-fabricated SiNWs. Fourier transform infrared spectroscopy was used to extract the bonding information for SiNWs. Electrical properties were evaluated using two-probe source measuring unit. Resistivity of 0.11 Ω-cm was obtained for synthesised SiNWs. A cost-effective, environment friendly electroless metal assisted chemical etching process was used to successfully develop SiNWs from the bulk Silicon wafer.

In this paper we present a new methodology to calibrate and correct in line roughness measurements for Silicon Nano Wires (SiNW) fabrication processes. For successful implementation of these processes in industry, the Silicon Nano Wires (SiNW) with widths of 5–25 nm should be characterized in the framework of Secondary Electron Microscope(CD SEM) Metrology. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range[1]. Such small differences in roughness values provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5–25 nm and roughness of 0–1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and CD metrics.

Theoretical study and software simulation on the sensitivity of silicon nanowires (SiNWs) field effect transistor (FET) sensors in terms of surface-to-volume ratio, depletion ratio, surface state and lattice quality are carried out. Generally, SiNWs-FET sensors with triangular cross-sections are more sensitive than sensors with circular or square cross-sections. Two main reasons are discussed in this article. Firstly, SiNWs-FET sensors with triangular cross-sections have the largest surface-to-volume ratio and depletion ratio which significantly enhance the sensors’ sensitivity. Secondly, the manufacturing processes of the electron beam lithography (EBL) and chemical vapor deposition (CVD) methods seriously affect the surface state and lattice quality, which eventually influence SiNWs-FET sensors’ sensitivity. In contrast, wet etching and thermal oxidation (WETO) create fewer surface defects and higher quality lattices. Furthermore, the software simulation confirms that SiNWs-FET sensors with triangular cross-sections have better sensitivity than the other two types of SiNWs-FET sensors under the same conditions, consistent with the theoretical analysis. The article fully proved that SiNWs-FET sensors fabricated by the WETO method produced the best sensitivity and it will be widely used in the future.

Semiconducting nanowires can be grown epitaxially on crystalline substrates in predefined directions. This bottom up approach stands in contrast to the common <i>top down</i> technology in semiconductor industry. With diameters down to a few nanometers, the nanowires’ small dimensions open up new possibilities for sensors and electronic devices. This thesis deals with the electrical, mechanical, and electromechanical characterization of silicon and zinc oxide nanowires. Their small dimensions reveal difficulties for the investigation of their properties. Common methods are used when possible, and new techniques are developed where standard methods reach their limits. The doping concentration of nanowires doped during growth is measured by contacting them using electron beam lithography. It is shown that by adding phosphine or diborane to the growth chamber, <i>n</i> and <i>p</i> doping concentrations in the order of 10¹⁹ cm⁻³ can be achieved. A careful analysis reveals that the doping concentration changes along the nanowire axis. <i>p-n</i> junctions along the nanowire axis are achieved by ion implantation after the nanowire growth. Because of the limited penetration depth of the dopant ions, this new doping process applies to rather short nanowires (<500 nm), only, so it is difficult to contact them by electron beam lithography. Alternatively, a novel method allowing the location of junctions at the nanometer scale is introduced. This method is based on a nanomanipulator built into a scanning electron microscope that is used to contact the nanowires, and the <i>p-n</i> doping profile is revealed by electron beam induced current imaging. The presented technique is able to qualitatively demonstrate the effective doping of very short individual nanowires. The nanomanipulator inside the scanning electron microscope used for the electrical investigations was originally developed to manipulate the nanowires for mechanical characterizaition. In contrast to traditional characterization techniques based on atomic force microscopy, a versatile tool is introduced that allows for fast characterization of nanostructures with real time visual feedback from the scanning electron microscope. In particular, tensile experiments can be performed in which the specimen is strained uniformly. This is important to reduce the influence of surface effects, for example when measuring Young’s modulus of a material. In order to precisely and automatically extract data from the experiments, an image analysis tool is programmed that can track objects with subpixel resolution. Further, finite element calculations show within which limits the analytic elastic beam formula can be used to calculate the maximum strain at the nanowire footing, taking into account its particular shape and the nanowires low aspect ratio. Mechanical investigations reveal that the fracture strength of both silicon and zinc oxide nanowires is close to the theoretical limit. Subjected to bending experiments, silicon and zinc oxide nanowires show a fracture strain of (6.3±1.8)% and (7.7±0.8)% (average ± 1 standard deviation), respectively. Because of the controversial values published on Young’s modulus of zinc oxide nanowires, these are subjected to tensile load as well. The tensile strength is 4 GP a, and Young’s modulus is measured to be 100 GPa, close to the bulk value of 144 GPa. Finally, an experiment for the measurement of electromechanical properties of silicon nanowires is proposed. It shows that the nanowires can be strained close to their fracture limit while measuring the electrical properties. We expect that the new measurement techniques developed in this work can be applied to a large number of different nanowires and microstructures, speeding up characterization and thus contributing to an efficient development of new materials and devices.

An electron beam (EB) lithography method using inedible cellulose-based resist material derived from woody biomass has been successfully developed. This method allows the use of pure water in the development process instead of the conventionally used tetramethylammonium hydroxide and anisole. The inedible cellulose-based biomass resist material, as an alternative to alpha-linked disaccharides in sugar derivatives that compete with food supplies, was developed by replacing the hydroxyl groups in the beta-linked disaccharides with EB-sensitive 2-methacryloyloxyethyl groups. A 75 nm line and space pattern at an exposure dose of 19 μC/cm2, a resist thickness uniformity of less than 0.4 nm on a 200 mm wafer, and low film thickness shrinkage under EB irradiation were achieved with this inedible cellulose-based biomass resist material using a water-based development process.

In recent years, silicon nanowires have become a hot spot in the new material industry. As a kind of nanomaterial, silicon nanowires have excellent physical and chemical properties. However, the preparation method of silicon nanowires is not mature enough, which limits its further application. This paper mainly analyses the mechanism, advantages and disadvantages of several mainstream silicon nanowires preparation methods, and discusses the application of silicon nanowires and the future development direction. The results show that the chemical vapor deposition method can be used for large-scale preparation of silicon nanowires, while the laser ablation method can produce silicon nanowires with higher purity, and the electron beam lithography method has the advantages of high flexibility. However, the efficiency of these three methods is not high, and the cost is high, which is also the problem that the silicon nanowire preparation industry is looking forward to solve. Relying on the excellent conductivity, thermal conductivity and other characteristics of silicon nanowires, silicon nanowires can be applied to a variety of new energy industries. Based on the properties of silicon nanowires, this paper analyses the application of silicon nanowires in lithium batteries, solar cells, biosensors and thermoelectric materials in recent years, and forecasts its development trend, so as to provide a certain reference for researchers to further explore the research of silicon nanowires.

A recent breakthrough in nanotechnology provides a great extent in sensor fabrication and application. The technology has emerged as a powerful technique to minimize the size of devices; amount of materials, energy and time consumption. Nanogap based sensor is one of the sensor that capable of characterizing and quantifying molecules selectively and sensitively with good electrical behavior. In this manuscript, we present a collaboration work between UniMAP, MARDI and UPM in the process development of 40 nm silicon nanogap for sensor application. The process consists of a combination of electron beam lithography (EBL) method and conventional photolithography method. Both methods were for nanogap and electrodes pattern respectively. Silicon on insulator (SOI) substrate was used to fabricate the nanogap structure and gold was used for the electrode. The ability of EBL system to fabricate a gap in nanometer scale with direct lithography technique on SOI substrate gives advantages in this development work. The developed silicon nanogap device was physically characterized with scanning electron microscope (SEM). The sensor application was accomplished by testing the device with different level of pH solutions using a dielectric analyzer.

This paper reports a comprehensive study on the fabrication of titanium dioxide-based memristors, patterned using electron beam lithography method. Memristor, one of the state-of-the-art technology devices with non-volatile memory, has gained significant attention in recent years. The properties of the memristor, such as non-volatility, high speed, and low cost, allow it to simplify memory and storage hierarchy. Hence, they are ideal for performing bioinspired neural networks through their ability to combine memory and computation in one physical structure. For memristors to be used as an electronic component in various applications, it is necessary to go beyond laboratory research studies. Therefore, it is essential to develop the fabrication process so as to enable the mass production of these devices. In this context, various optimization studies were carried out primarily to provide that the structures of memristor successfully show memristive behavior during the fabrication process steps. Throughout the fabrication process, the bottom electrode, active layer, and top electrode of memristors were patterned by using electron beam lithography. In addition, the sputtering method is used for the deposition of electrodes, and the atomic layer deposition method is used for the active layer. Following the fabrication process, scanning electron microscopy is used to characterize the surface properties of the memristor structure. Current-voltage measurements were carried out to characterize the electrical behaviors of memristors and to test their endurance. As a result of measurements, the fabricated devices have shown memristive behavior successfully and good endurance for 1000 cycles.

Surface enhanced Raman scattering (SERS) substrates are expected to be applied to some functional devices such as high-sensitive biosensors and photocatalysts.[1-2] In order to produce metal nanostructures, electron beam lithography and chemical method have mainly been used so far. Although these methods are effective for nano-level microfabrication, there are problems such as the need for multiple processes, unsuitability for large-area processing, poor mass production, and susceptibility to surface oxidation. For clearing these problems, we have fabricated SERS substrates by depositing metal nanostructures on MgO(001) substrates using the pulsed laser ablation (PLA) method,[3] which is a one-step fabrication process. In previous research, we produced gold nanostructures by using PLA[4]. The wavelength of plasmon resonances due to the gold nanostructures exhibited in the infrared region, and therefore laser beam with 785 nm was utilized to SERS and Raman spectroscopy. We observed significant strong SERS signals after applying the gold nanostructures to SERS substrates. However, we also observed strong Raman signals due to the MgO(001) substrate, resulting in a spectrum where the SERS signals and the Raman signals interfering. To reduce the Raman signal due to the MgO(001) substrate, it is necessary to decrease a wavelength of an excitation laser which is equipped with the Raman system because the penetration depth of the laser beam into the MgO(001) substrate becomes shallower. Therefore, we focused on silver nanostructures because the wavelength of plasmon resonances was shorter than those of gold. The SERS substrates, which consists in silver nanostructures on MgO(001) substrate, expects to resonate with visible light. Consequently, the SERS signals will be generated to irradiate a laser beam with 532 nm, leading to reduce the Raman signals due to MgO(001) substrate. In this study, silver nanostructures with plasmon resonance wavelengths in the visible light region were fabricated by the PLA method. Silver nanostructures are deposited on a MgO(001) substrate (Furuuchi; size: 10×10mm2 and thickness: 0.5mm) by PLA. A Silver target (Furuuchi; diameter: 13mm, 99.99%) and MgO(001) substrate were located on a vacuumed chamber. The chamber was pumped down to 10-5 Torr and the substrate was treated by outgas (350℃, 30min) and cleaning (800℃, 30min) using a silicon-carbide heating system. After cleaning, the deposition temperature was set to 350 ℃, 450 ℃ and 550 ℃. Argon or oxygen gas was flowed in the vacuum chamber. A pulsed laser beam (LOTIS TII, LS-2147: wavelength: 355 nm, pulse width: 10 ns, laser fluence: 0.8 J/cm2, repetition frequency: 4 Hz, and number of laser pulses: 7000) was irradiated through a laser insertion window into the installed silver target. Silver nanostructures were fabricated by ablation plumes and depositing them on a MgO(001) substrate. Optical transmittance measurements of the silver nanostructures fabricated by the PLA method showed that they have an optical absorption peak in the visible light region around 600 nm. Surface observation by using an atomic force microscopy (AFM: Hitachi High-Tech, SPA 300, dynamic force mode) showed self-grown nanoparticles with edges and silver nanostructures was observed Ag (200) by a high angle x-ray diffraction (XRD: Rigaku, RINT2000). SERS measurements were carried out using 4-MBA, and a SERS substrate with an enhancement factor of 5.51×105 was successfully developed.

One dimensional silicon nanostructures have attracted remarkable attentions due to their unique electronic, optoelectronic and thermal properties [1]. Recently, silicon nanowires (SiNWs) become the promising architecture in the present miniaturization of silicon-based devices, enabling many potential applications such as field-effect transistors (FET) [2], optoelectronics [3] and solar cells [3, 4]. In fact, the most crucial step to address the practical applications based on SiNWs is the control over dimensions, crystallographic orientation and doping level for the formation of SiNWs. These issues remain particularly challenging for constructing the complex SiNW- based devices [8] or integration of multifunctional elements [9], and one promising solution is the controlled synthesis of ultra-long SiNWs with uniform structure and properties which has been reported by W. Park et al [10]. So far, great efforts have been made to fabricate the ultra-long SiNWs, including thermal evaporation [11] and vapor- liquid- solid (VLS) growth [10]. Nevertheless, those aforementioned approaches involve serve vacuum condition, high process temperature and preparation of catalytic materials, leading the entire processes to be quite expensive and complex [10, 11] and incapable of fabricating a large area of well- aligned SiNW arrays. As a consequence, we report the fabrication of single crystalline SiNW arrays with uniform length up to 450 μm via modified electroless metal deposition (EMD) method [12]. The utilization of conventional EMD method to fabricate ordered SiNW arrays is rather simple and inexpensive, in which the entire processes are carried out by mean of immersing silicon wafer into HF/ AgNO3 electrolyte solution at near room temperature. Nevertheless, we find that the succeeding formation of SiNWs via typical EMD approach is prohibited from the abundant Ag dendrites covering on the surface of SiNWs, impeding the controllability of SiNWs lengths over 250 μm [13-17]. To overcome it, the diluted HNO3 solution is introduced in EMD method to render the continuity of galvanic reaction, enabling the fabrication of wafer- scale well- aligned SiNW arrays with desired length ranging from several up to hundreds micrometers and even approaching to the thickness of used Si substrate Indeed, the diameter of formed Si nanowire cannot be adjusted by using the conventional EMD method because multiple process factors are involved simultaneously in its galvanic reaction, so that their diameter has a wide distribution from 10 to 500 nm. Besides, SiNW-based structures are widely employed in diverse field and the high performance devices of SiNW are crucial to its diameter, especially the electrical and optical properties of SiNWs are strongly size dependent. Recently, researchers are effortfully searching for the appropriate diameter range of SiNWs to attain the corresponding optimal applications. Specifically, SiNWs smaller than 100 nm in diameter may be used in high-speed quantum-wire field effect transistors and light-emitting devices with extremely low power consumption [18], and SiNWs with width <150 nm are virtually sensitive to detect threshold shifts between buffer solutions of different pH [19]. On the contrary, the unique property such as, the independence of elastic modulus from their structure diameter [20] and a polarization-independent response in the building block for photovoltaic systems [21] are also exhibited if the diameter larger than 100 nm. In general, an average SiNW diameter of approximately 100 nm achieves satisfactorily their properties as mention above. Therefore, we apply Response Surface Methodology (RSM), a collection of statistical and mathematical techniques, for finding out the optimization of the response with the lowest standard deviation in order to fabricate 1D Silicon structures with 100 nm in diameter.

Synthesis of ordered Si nanowire arrays in porous anodic aluminum oxide templates

The realization of reliable nanobiosensor devices requires the improvement of fabrication techniques to form the nanometer-sized structures and patterns, which were used to attach nano materials such as DNA for the device elements. This study demonstrates the sensitivity of silicon nanowires (SiNWs) as a sensing element in sensor application. Starting with silicon on insulator (SOI) material, the SiNWs with &lt;100nm in width were fabricated using electron beam lithography combined with conventional CMOS process. Different numbers of SiNWs which are single, 10 arrays of nanowires and 20 arrays of nanowires were developed. Subsequently, the two metal electrodes which are designated as source (S) and drain (D) were fabricated on top of individual SiNWs using optical lithography process. Optical and electrical characteristic have been proposed to verify the outcome of the fabricated structures. One major part is to observe the SiNWs optically in order to meet the nano-scale variation by using High Power Microscope (HPM) inspection and Field Emission Scanning Electron Microscope (FESEM) imaging. Finally, the samples will be tested electrically using I-V measurement system. The results show that device with single SiNW with 60nm in width give the highest resistivity value due to surface to volume ratio.