Abstract
In the paper, the folded-cascode low-noise operational amplifier (LNA) with constant-gm is proposed and analyzed. The channel-length split technique adopted to expand ratio of W/L of the differential pair transistor to improve the performance of LNA for the gain bandwidth product, noise and offset voltage. The channel-length split method is separated differential input transistor into 2 transistors in series. The area of the transistor (W, L) can be properly increased to effectively decrease the flick noise. The double indirect-frequency compensation technique and the clamping circuit are adopted in amplifier to increase the bandwidth. The proposed two sets input differential pair can be provided a constant-gm value and rail-to-rail swing during the operating region. The floating-point structure is used to reach rail-to-rail swing at output stage. Simulation results show that the gain, constant-gm in input stag, noise, offset-voltage, PSRR, CMRR and ICMR of amplifier are improved. The characteristics of LNA are successfully verified by the TSMC 0.35um 2P4M CMOS technology. There have a great potential in the VLSI implementation used in the portable electronic and bio-medicine product applications.
Highlights
The low noise amplifier (LNA) is a one of important device in the analog circuit which is used in communication, high-frequency, and the required high-precision circuit applications
The channel-split used in PMOS and NMOS differential pairs are split to two transistors in serial that the node E and F to form low-impedance point is shown in Fig. (6)
To verify the validity of the proposed LNA, the amplifier is simulated by HSPICE for CMOS technology
Summary
The low noise amplifier (LNA) is a one of important device in the analog circuit which is used in communication, high-frequency, and the required high-precision circuit applications. The transistor is adopted larger width to improve the noise and make the frequency response become to poor. Using channel length split technique to reduce the gate-channel capacitance to reach the band-width improved. The channel-length split method is separated differential input transistor into 2 transistors in series, is shown in Fig. The channel-length split technique is reduced the total capacitance to improve the frequency response and take high gain. The channel-split used in PMOS and NMOS differential pairs are split to two transistors in serial that the node E and F to form low-impedance point is shown in Fig. The amplifier applied the channel-split and the indirect compensation has the higher gain-bandwidth multiplication at low-noise
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