Threshold voltage shift of heteronanocrystal floating gate flash memory

Abstract

Simulations of threshold voltage shift of a p-channel Ge/Si heteronanocrystal floating gate memory device were carried out using both a numerical two-dimensional Poisson–Boltzmann method and an equivalent circuit model. The results show that the presence of a Ge dot on top of a Si dot significantly prolongs the retention time of the device, indicated by the time decay behavior of the threshold voltage shift. Both methods lead to consistent results that an increase in the thickness of either the Si dot or Ge dot will result in a reduction of the threshold voltage shift. Additionally, the threshold voltage shift increases significantly as the heteronanocrystal density increases. Nevertheless, only a weak dependence of threshold voltage shift on the tunneling oxide thickness was found.