Abstract
Thermally stable tungsten (W) bit-line process technology has been successfully integrated for capacitor over bit-line (COB)-type dynamic random-access memory (DRAM). Major parameters of the W bit-line process flow are demonstrated to be the Ti thickness, the silicidation temperature and the dopant concentration. The minimum contact resistance (<1000 Ω) of the W bit-line into the p+ active region has been obtained by the silicidation of thin Ti (7 nm) at a high temperature (800°C) with the additional ion implantation of BF2+ after the contact formation. The effects of the process parameters were explained in terms of the agglomeration of the Ti silicide and dopant concentration in the silicon active region.
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