Thermal Assessment and Enhancement of Molded Array (MAP) PBGA Packages for Handheld Telecommunication Applications

Abstract

Abstract Computational Fluid Dynamics (CFD) simulations were conducted to characterize the thermal performance of Molded Array Plastic Ball Grid Array (MAP PBGA) packages for hand-held applications. Due to size constraints, these PBGA packages tend to have fine pitch solder ball arrays and small overall size. Thermal analysis is required to assess the design risks associated with this trend toward smaller size and increasing power dissipation requirements. A conjugate heat transfer problem, in which radiative losses from the exposed surfaces of the package and the printed wiring board to the walls of the wind tunnel, was solved for horizontal natural convection cooling conditions. Thermal model assumptions and development for the MAP PBGA package are provided. The model is benchmarked with measurements obtained for a 64 I/O 0.8 mm pitch, 8 mm MAP PBGA. Predictions for junction-to-ambient thermal resistance were within 10% of measured values. Baseline simulations were conducted for 0.8 mm pitch MAP PBGA packages with substrate/die size combinations in the range of 6 to 12 mm substrate size and 3.81 to 7.62 mm die size. Junction-to-ambient thermal resistances varied over the range of 28.8 °C/W to 62.4 °C/W. Methods to improve thermal performance of these packages were investigated. Previous work indicated that effective conduction to the substrate by heat spreaders, metallic lids, mold compound, heat sinks, and their combinations promoted thermal performance. A necessary further step is to understand how effective area for heat spreading inside the package affects its thermal behavior, while varying the die size for package configurations with and without heat spreader. Studies were conducted to evaluate thermal performance improvement through the use of a copper heat spreader on the package top surface as it is affected by die size, package size, and substrate effective thermal conductivity. Substrate effective thermal conductivity is varied through the use of two and four layer substrates with thermal vias under the die. Results show a modest 1% to 15% reduction in junction-to-ambient thermal resistance for the MAP PBGA package sizes of interest.