Thermal analysis of 4H-SiC DMOSFET structure under resistive switching

Abstract

This research investigates the electro-thermal switching characteristics and lattice temperature profile of a two dimensional (2D) silicon carbide (4H-SiC polytype) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell under resistive switching using Silvaco ATLAS Technology Computer Aided Design (TCAD) physics based simulation software. Physics based models were included to account for recombination effects, bandgap narrowing, low field and high field mobility and lattice heating. The electro-thermal simulation was performed at an ambient lattice temperature of 300K. The device was simulated for 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 1000 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> drain current densities using a 1 kHz 50% duty cycle gate signal consisting of two cycles and 1.6 kHz 80% duty cycle signal consisting of three cycles. The analysis of lattice temperature profile revealed the formation of thermal hot spots in the vicinity of the (Junction Field Effect Transistor) JFET region in the DMOSFET structure during the switching phase and at the edge of the channel during the conduction phase. The magnitude of temperature rise was dependent on the drain current density used during the simulation.