Abstract
Functional validation is a major bottleneck in hardware design. Two main approaches to ensure functional correctness of hardware systems are based on formal verification and simulation techniques. It is widely recognized that formal verification techniques are exhaustive but do not scale well; simulation-based techniques are scalable but are not exhaustive. Possible compromise is provided by semi-formal approaches combining formal specifications, functional coverage definition, and simulation. This paper describes the UniTESK approach to specification-based validation of hardware designs in which a good balance of exhaustiveness and scalability is found. UniTESK is originally intended for the development of high-quality functional tests for software systems. The paper shows how to adapt it for functional validation of Verilog HDL and SystemC designs.
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